594 static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,  in cmu_wr()  function
632 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_toggle1to0()
635 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_toggle1to0()
645 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_clrbits()
655 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_setbits()
713 	cmu_wr(ctx, cmu_type, CMU_REG12, val);  in xgene_phy_cfg_cmu_clk_type()
715 	cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222);  in xgene_phy_cfg_cmu_clk_type()
716 	cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225);  in xgene_phy_cfg_cmu_clk_type()
723 		cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_cfg_cmu_clk_type()
727 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
733 		cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_cfg_cmu_clk_type()
737 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
748 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
752 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
772 		cmu_wr(ctx, cmu_type, CMU_REG34, val);  in xgene_phy_sata_cfg_cmu_core()
781 	cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_sata_cfg_cmu_core()
794 	cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_sata_cfg_cmu_core()
818 	cmu_wr(ctx, cmu_type, CMU_REG2, val);  in xgene_phy_sata_cfg_cmu_core()
833 	cmu_wr(ctx, cmu_type, CMU_REG3, val);  in xgene_phy_sata_cfg_cmu_core()
838 	cmu_wr(ctx, cmu_type, CMU_REG26, val);  in xgene_phy_sata_cfg_cmu_core()
848 	cmu_wr(ctx, cmu_type, CMU_REG5, val);  in xgene_phy_sata_cfg_cmu_core()
854 	cmu_wr(ctx, cmu_type, CMU_REG6, val);  in xgene_phy_sata_cfg_cmu_core()
868 		cmu_wr(ctx, cmu_type, CMU_REG9, val);  in xgene_phy_sata_cfg_cmu_core()
873 			cmu_wr(ctx, cmu_type, CMU_REG10, val);  in xgene_phy_sata_cfg_cmu_core()
884 	cmu_wr(ctx, cmu_type, CMU_REG16, val);  in xgene_phy_sata_cfg_cmu_core()
890 	cmu_wr(ctx, cmu_type, CMU_REG30, val);  in xgene_phy_sata_cfg_cmu_core()
893 	cmu_wr(ctx, cmu_type, CMU_REG31, 0xF);  in xgene_phy_sata_cfg_cmu_core()
901 	cmu_wr(ctx, cmu_type, CMU_REG32, val);  in xgene_phy_sata_cfg_cmu_core()
905 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27);  in xgene_phy_sata_cfg_cmu_core()
907 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c);  in xgene_phy_sata_cfg_cmu_core()
910 	cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F);  in xgene_phy_sata_cfg_cmu_core()
921 	cmu_wr(ctx, cmu_type, CMU_REG35, val);  in xgene_phy_ssc_enable()
928 	cmu_wr(ctx, cmu_type, CMU_REG36, val);  in xgene_phy_ssc_enable()
1157 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cal_rdy_chk()
1184 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1195 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1202 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1245 		cmu_wr(ctx, cmu_type, CMU_REG16, val);  in xgene_phy_pdwn_force_vco()