28  * indirectly from the SDS offset at 0x2000. It is only required for
30  * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
31  * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
36  * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
53 #define SERDES_PLL_INDIRECT_OFFSET	0x0000
54 #define SERDES_PLL_REF_INDIRECT_OFFSET	0x2000
55 #define SERDES_INDIRECT_OFFSET		0x0400
56 #define SERDES_LANE_STRIDE		0x0200
59 #define DEFAULT_SATA_TXBOOST_GAIN	{ 0x1e, 0x1e, 0x1e }
60 #define DEFAULT_SATA_TXEYEDIRECTION	{ 0x0, 0x0, 0x0 }
61 #define DEFAULT_SATA_TXEYETUNING	{ 0xa, 0xa, 0xa }
62 #define DEFAULT_SATA_SPD_SEL		{ 0x1, 0x3, 0x7 }
63 #define DEFAULT_SATA_TXAMP		{ 0x8, 0x8, 0x8 }
64 #define DEFAULT_SATA_TXCN1		{ 0x2, 0x2, 0x2 }
65 #define DEFAULT_SATA_TXCN2		{ 0x0, 0x0, 0x0 }
66 #define DEFAULT_SATA_TXCP1		{ 0xa, 0xa, 0xa }
68 #define SATA_SPD_SEL_GEN3		0x7
69 #define SATA_SPD_SEL_GEN2		0x3
70 #define SATA_SPD_SEL_GEN1		0x1
72 #define SSC_DISABLE			0
75 #define FBDIV_VAL_50M			0x77
76 #define REFDIV_VAL_50M			0x1
77 #define FBDIV_VAL_100M			0x3B
78 #define REFDIV_VAL_100M			0x0
81 #define SATACLKENREG			0x00000000
82 #define  SATA0_CORE_CLKEN		0x00000002
83 #define  SATA1_CORE_CLKEN		0x00000004
84 #define SATASRESETREG			0x00000004
85 #define  SATA_MEM_RESET_MASK		0x00000020
86 #define  SATA_MEM_RESET_RD(src)		(((src) & 0x00000020) >> 5)
87 #define  SATA_SDS_RESET_MASK		0x00000004
88 #define  SATA_CSR_RESET_MASK		0x00000001
89 #define  SATA_CORE_RESET_MASK		0x00000002
90 #define  SATA_PMCLK_RESET_MASK		0x00000010
91 #define  SATA_PCLK_RESET_MASK		0x00000008
94 #define SATA_ENET_SDS_PCS_CTL0		0x00000000
96 		(((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
98 		(((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
99 #define SATA_ENET_SDS_CTL0		0x0000000c
101 		(((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
102 #define SATA_ENET_SDS_CTL1		0x00000010
104 		(((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
105 #define SATA_ENET_SDS_RST_CTL		0x00000024
106 #define SATA_ENET_SDS_IND_CMD_REG	0x0000003c
107 #define  CFG_IND_WR_CMD_MASK		0x00000001
108 #define  CFG_IND_RD_CMD_MASK		0x00000002
109 #define  CFG_IND_CMD_DONE_MASK		0x00000004
111 		(((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
112 #define SATA_ENET_SDS_IND_RDATA_REG	0x00000040
113 #define SATA_ENET_SDS_IND_WDATA_REG	0x00000044
114 #define SATA_ENET_CLK_MACRO_REG		0x0000004c
116 		(((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
118 		(((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
120 		(((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
121 #define  O_PLL_LOCK_RD(src)		(((src) & 0x40000000) >> 30)
122 #define  O_PLL_READY_RD(src)		(((src) & 0x80000000) >> 31)
125 #define CMU_REG0			0x00000
126 #define  CMU_REG0_PLL_REF_SEL_MASK	0x00002000
128 		(((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
129 #define  CMU_REG0_PDOWN_MASK		0x00004000
131 		(((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
132 #define CMU_REG1			0x00002
134 		(((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
136 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
138 		(((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
139 #define  CMU_REG1_REFCLK_CMOS_SEL_MASK	0x00000001
141 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
142 #define CMU_REG2			0x00004
144 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
146 		(((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
148 		(((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
149 #define CMU_REG3			0x00006
151 		(((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
153 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
155 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
156 #define CMU_REG4			0x00008
157 #define CMU_REG5			0x0000a
159 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
161 		(((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
163 		(((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000))
164 #define  CMU_REG5_PLL_RESETB_MASK	0x00000001
165 #define CMU_REG6			0x0000c
167 		(((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600))
169 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
170 #define CMU_REG7			0x0000e
171 #define  CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14)
172 #define  CMU_REG7_VCO_CAL_FAIL_RD(src)	((0x00000c00 & (u32) (src)) >> 10)
173 #define CMU_REG8			0x00010
174 #define CMU_REG9			0x00012
175 #define  CMU_REG9_WORD_LEN_8BIT		0x000
176 #define  CMU_REG9_WORD_LEN_10BIT	0x001
177 #define  CMU_REG9_WORD_LEN_16BIT	0x002
178 #define  CMU_REG9_WORD_LEN_20BIT	0x003
179 #define  CMU_REG9_WORD_LEN_32BIT	0x004
180 #define  CMU_REG9_WORD_LEN_40BIT	0x005
181 #define  CMU_REG9_WORD_LEN_64BIT	0x006
182 #define  CMU_REG9_WORD_LEN_66BIT	0x007
184 		(((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380))
186 		(((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070))
188 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
190 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
192 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
193 #define CMU_REG10			0x00014
195 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
196 #define CMU_REG11			0x00016
197 #define CMU_REG12			0x00018
199 		(((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
200 #define CMU_REG13			0x0001a
201 #define CMU_REG14			0x0001c
202 #define CMU_REG15			0x0001e
203 #define CMU_REG16			0x00020
204 #define  CMU_REG16_PVT_DN_MAN_ENA_MASK	0x00000001
205 #define  CMU_REG16_PVT_UP_MAN_ENA_MASK	0x00000002
207 		(((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
209 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
211 		(((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
212 #define CMU_REG17			0x00022
214 		(((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00))
216 		(((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
217 #define  CMU_REG17_PVT_TERM_MAN_ENA_MASK	0x00008000
218 #define CMU_REG18			0x00024
219 #define CMU_REG19			0x00026
220 #define CMU_REG20			0x00028
221 #define CMU_REG21			0x0002a
222 #define CMU_REG22			0x0002c
223 #define CMU_REG23			0x0002e
224 #define CMU_REG24			0x00030
225 #define CMU_REG25			0x00032
226 #define CMU_REG26			0x00034
228 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
229 #define CMU_REG27			0x00036
230 #define CMU_REG28			0x00038
231 #define CMU_REG29			0x0003a
232 #define CMU_REG30			0x0003c
234 		(((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
236 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
237 #define CMU_REG31			0x0003e
238 #define CMU_REG32			0x00040
239 #define  CMU_REG32_FORCE_VCOCAL_START_MASK	0x00004000
241 		(((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
243 		(((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180))
244 #define CMU_REG33			0x00042
245 #define CMU_REG34			0x00044
247 		(((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
249 		(((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00))
251 		(((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
253 		(((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
254 #define CMU_REG35			0x00046
256 		(((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
257 #define CMU_REG36				0x00048
259 		(((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
261 		(((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0))
263 		(((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
264 #define CMU_REG37			0x0004a
265 #define CMU_REG38			0x0004c
266 #define CMU_REG39			0x0004e
269 #define RXTX_REG0			0x000
271 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
273 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
275 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
276 #define RXTX_REG1			0x002
278 		(((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
280 		(((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
282 		(((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
284 		(((dst) & ~0x00000006) | (((u32) (src) << 1) &  0x00000006))
285 #define RXTX_REG2			0x004
287 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
289 		(((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
291 		(((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
292 #define RXTX_REG4			0x008
293 #define  RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK	0x00000040
295 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
297 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
298 #define RXTX_REG5			0x00a
300 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
302 		(((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0))
304 		(((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f))
305 #define RXTX_REG6			0x00c
307 		(((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780))
309 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
311 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
313 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
315 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
316 #define RXTX_REG7			0x00e
317 #define  RXTX_REG7_RESETB_RXD_MASK	0x00000100
318 #define  RXTX_REG7_RESETB_RXA_MASK	0x00000080
320 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
322 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
323 #define RXTX_REG8			0x010
325 		(((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
327 		(((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800))
329 		(((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200))
331 		(((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
333 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
334 #define RXTX_REG7			0x00e
336 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
338 		(((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
339 #define  RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK	0x00004000
341 		(((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
342 #define RXTX_REG11			0x016
344 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
345 #define RXTX_REG12			0x018
347 		(((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
349 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
350 #define  RXTX_REG12_RX_DET_TERM_ENABLE_MASK	0x00000002
352 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
353 #define RXTX_REG13			0x01a
354 #define RXTX_REG14			0x01c
356 		(((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f))
358 		(((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
359 #define RXTX_REG26			0x034
361 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
363 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
364 #define RXTX_REG21			0x02a
365 #define  RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
366 #define  RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
367 #define  RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src)	((0x0000000f & (u32)(src)))
368 #define RXTX_REG22			0x02c
369 #define  RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
370 #define  RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
371 #define  RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src)	((0x0000000f & (u32)(src)))
372 #define RXTX_REG23			0x02e
373 #define  RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
374 #define  RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
375 #define RXTX_REG24			0x030
376 #define  RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
377 #define  RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
378 #define RXTX_REG27			0x036
379 #define RXTX_REG28			0x038
380 #define RXTX_REG31			0x03e
381 #define RXTX_REG38			0x04c
383 		(((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
384 #define RXTX_REG39			0x04e
385 #define RXTX_REG40			0x050
386 #define RXTX_REG41			0x052
387 #define RXTX_REG42			0x054
388 #define RXTX_REG43			0x056
389 #define RXTX_REG44			0x058
390 #define RXTX_REG45			0x05a
391 #define RXTX_REG46			0x05c
392 #define RXTX_REG47			0x05e
393 #define RXTX_REG48			0x060
394 #define RXTX_REG49			0x062
395 #define RXTX_REG50			0x064
396 #define RXTX_REG51			0x066
397 #define RXTX_REG52			0x068
398 #define RXTX_REG53			0x06a
399 #define RXTX_REG54			0x06c
400 #define RXTX_REG55			0x06e
401 #define RXTX_REG61			0x07a
403 		(((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
405 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
407 		(((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
409 		(((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
410 #define RXTX_REG62			0x07c
412 		(((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
413 #define RXTX_REG81			0x0a2
415 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
417 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
419 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
420 #define RXTX_REG96			0x0c0
422 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
424 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
426 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
427 #define RXTX_REG99			0x0c6
429 		(((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
431 		(((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
433 		(((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
434 #define RXTX_REG102			0x0cc
436 		(((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
437 #define RXTX_REG114			0x0e4
438 #define RXTX_REG121			0x0f2
439 #define  RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1)
440 #define RXTX_REG125			0x0fa
442 		(((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
444 		(((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
446 		(((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
448 		(((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
450 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
451 #define RXTX_REG127			0x0fe
452 #define  RXTX_REG127_FORCE_SUM_CAL_START_MASK	0x00000002
453 #define  RXTX_REG127_FORCE_LAT_CAL_START_MASK	0x00000004
455 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
457 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
459 		(((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
461 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
463 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
464 #define RXTX_REG128			0x100
466 		(((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
468 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
470 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
471 #define RXTX_REG129			0x102
473 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
475 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
476 #define RXTX_REG130			0x104
478 		(((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
480 		(((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
481 #define RXTX_REG145			0x122
483 		(((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
485 		(((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
487 		(((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
489 		(((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
490 #define RXTX_REG147			0x126
491 #define RXTX_REG148			0x128
495 	REF_CMU = 0,	/* Clock macro is the internal reference clock */
500 	MUX_SELECT_ATA = 0,	/* Switch the MUX to ATA */
501 	MUX_SELECT_SGMMII = 0,	/* Switch the MUX to SGMII */
505 	CLK_EXT_DIFF = 0,	/* External differential */
511 	MODE_SATA	= 0,	/* List them for simple reference */
548 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
569 		pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",  in sds_wr()
590 		pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",  in sds_rd()
608 	pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val);  in cmu_wr()
622 	pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data);  in cmu_rd()
669 	pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data,  in serdes_wr()
681 	pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data);  in serdes_rd()
712 	val = CMU_REG12_STATE_DELAY9_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
715 	cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222);  in xgene_phy_cfg_cmu_clk_type()
716 	cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225);  in xgene_phy_cfg_cmu_clk_type()
722 		val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
726 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
732 		val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
736 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
747 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);  in xgene_phy_cfg_cmu_clk_type()
751 		val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);  in xgene_phy_cfg_cmu_clk_type()
768 		val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
769 		val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc);  in xgene_phy_sata_cfg_cmu_core()
770 		val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
771 		val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8);  in xgene_phy_sata_cfg_cmu_core()
778 		val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
780 		val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
785 	val = CMU_REG1_PLL_CP_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
787 		val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5);  in xgene_phy_sata_cfg_cmu_core()
789 		val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
791 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
793 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
802 		val = CMU_REG2_PLL_LFRES_SET(val, 0xa);  in xgene_phy_sata_cfg_cmu_core()
805 		val = CMU_REG2_PLL_LFRES_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
807 			ref_100MHz = 0;  in xgene_phy_sata_cfg_cmu_core()
823 		val = CMU_REG3_VCOVARSEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
824 		val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10);  in xgene_phy_sata_cfg_cmu_core()
826 		val = CMU_REG3_VCOVARSEL_SET(val, 0xF);  in xgene_phy_sata_cfg_cmu_core()
828 			val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15);  in xgene_phy_sata_cfg_cmu_core()
830 			val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a);  in xgene_phy_sata_cfg_cmu_core()
831 		val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15);  in xgene_phy_sata_cfg_cmu_core()
837 	val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
842 	val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
843 	val = CMU_REG5_PLL_LFCAP_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
845 		val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
847 		val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
852 	val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2);  in xgene_phy_sata_cfg_cmu_core()
853 	val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0);  in xgene_phy_sata_cfg_cmu_core()
863 		val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
865 			val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
866 			val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0);  in xgene_phy_sata_cfg_cmu_core()
872 			val = CMU_REG10_VREG_REFSEL_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
878 	val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
879 	val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
881 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4);  in xgene_phy_sata_cfg_cmu_core()
883 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);  in xgene_phy_sata_cfg_cmu_core()
888 	val = CMU_REG30_PCIE_MODE_SET(val, 0x0);  in xgene_phy_sata_cfg_cmu_core()
889 	val = CMU_REG30_LOCK_COUNT_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
893 	cmu_wr(ctx, cmu_type, CMU_REG31, 0xF);  in xgene_phy_sata_cfg_cmu_core()
896 	val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
898 		val = CMU_REG32_IREF_ADJ_SET(val, 0x3);  in xgene_phy_sata_cfg_cmu_core()
900 		val = CMU_REG32_IREF_ADJ_SET(val, 0x1);  in xgene_phy_sata_cfg_cmu_core()
905 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27);  in xgene_phy_sata_cfg_cmu_core()
907 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c);  in xgene_phy_sata_cfg_cmu_core()
910 	cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F);  in xgene_phy_sata_cfg_cmu_core()
946 	for (lane = 0; lane < MAX_LANE; lane++) {  in xgene_phy_sata_cfg_lanes()
947 		serdes_wr(ctx, lane, RXTX_REG147, 0x6);  in xgene_phy_sata_cfg_lanes()
951 		val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
952 		val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
953 		val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
958 		val = RXTX_REG1_RXACVCM_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
968 		val = RXTX_REG2_VTT_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
969 		val = RXTX_REG2_VTT_SEL_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
970 		val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
980 			val = RXTX_REG1_RXVREG1_SET(val, 0x2);  in xgene_phy_sata_cfg_lanes()
981 			val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2);  in xgene_phy_sata_cfg_lanes()
1003 		val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1004 		val = RXTX_REG6_TX_IDLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1005 		val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1006 		val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1011 		val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1017 		val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1018 		val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1019 		val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1020 		val = RXTX_REG8_SD_DISABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1021 		val = RXTX_REG8_SD_VREF_SET(val, 0x4);  in xgene_phy_sata_cfg_lanes()
1026 		val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1031 		val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1032 		val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1033 		val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1038 		val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1039 		val = RXTX_REG26_BLWC_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1042 		serdes_wr(ctx, lane, RXTX_REG28, 0x0);  in xgene_phy_sata_cfg_lanes()
1045 		serdes_wr(ctx, lane, RXTX_REG31, 0x0);  in xgene_phy_sata_cfg_lanes()
1049 		val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1050 		val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1051 		val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1055 		val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1059 		for (i = 0; i < 9; i++) {  in xgene_phy_sata_cfg_lanes()
1062 			val = RXTX_REG89_MU_TH7_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1063 			val = RXTX_REG89_MU_TH8_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1064 			val = RXTX_REG89_MU_TH9_SET(val, 0xe);  in xgene_phy_sata_cfg_lanes()
1069 		for (i = 0; i < 3; i++) {  in xgene_phy_sata_cfg_lanes()
1072 			val = RXTX_REG96_MU_FREQ1_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1073 			val = RXTX_REG96_MU_FREQ2_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1074 			val = RXTX_REG96_MU_FREQ3_SET(val, 0x10);  in xgene_phy_sata_cfg_lanes()
1079 		for (i = 0; i < 3; i++) {  in xgene_phy_sata_cfg_lanes()
1082 			val = RXTX_REG99_MU_PHASE1_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1083 			val = RXTX_REG99_MU_PHASE2_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1084 			val = RXTX_REG99_MU_PHASE3_SET(val, 0x7);  in xgene_phy_sata_cfg_lanes()
1089 		val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1092 		serdes_wr(ctx, lane, RXTX_REG114, 0xffe0);  in xgene_phy_sata_cfg_lanes()
1101 		val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1105 		val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1109 		val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3);  in xgene_phy_sata_cfg_lanes()
1113 		val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3);  in xgene_phy_sata_cfg_lanes()
1114 		val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1116 			val = RXTX_REG145_RXES_ENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1117 			val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1);  in xgene_phy_sata_cfg_lanes()
1119 			val = RXTX_REG145_RXES_ENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1120 			val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0);  in xgene_phy_sata_cfg_lanes()
1128 		for (i = 0; i < 4; i++) {  in xgene_phy_sata_cfg_lanes()
1130 			serdes_wr(ctx, lane, reg, 0xFFFF);  in xgene_phy_sata_cfg_lanes()
1144 	writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL);  in xgene_phy_cal_rdy_chk()
1156 		val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1182 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12);  in xgene_phy_cal_rdy_chk()
1183 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1193 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29);  in xgene_phy_cal_rdy_chk()
1194 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1200 	val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28);  in xgene_phy_cal_rdy_chk()
1201 	val = CMU_REG17_RESERVED_7_SET(val, 0x0);  in xgene_phy_cal_rdy_chk()
1218 	} while (--loop > 0);  in xgene_phy_cal_rdy_chk()
1231 	dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not ");  in xgene_phy_cal_rdy_chk()
1232 	return 0;  in xgene_phy_cal_rdy_chk()
1244 		val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);  in xgene_phy_pdwn_force_vco()
1263 	writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL);  in xgene_phy_hw_init_sata()
1266 	writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL);  in xgene_phy_hw_init_sata()
1269 	writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL);  in xgene_phy_hw_init_sata()
1275 		ctx->sata_param.txspeed[ctx->sata_param.speed[0]]);  in xgene_phy_hw_init_sata()
1280 	val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421);  in xgene_phy_hw_init_sata()
1298 	val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3);  in xgene_phy_hw_init_sata()
1299 	val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3);  in xgene_phy_hw_init_sata()
1309 	} while (--i > 0);  in xgene_phy_hw_init_sata()
1311 	if (i <= 0)  in xgene_phy_hw_init_sata()
1314 	return 0;  in xgene_phy_hw_init_sata()
1335 	return 0;  in xgene_phy_hw_initialize()
1351 		{RXTX_REG38, 0x0},  in xgene_phy_force_lat_summer_cal()
1352 		{RXTX_REG39, 0xff00},  in xgene_phy_force_lat_summer_cal()
1353 		{RXTX_REG40, 0xffff},  in xgene_phy_force_lat_summer_cal()
1354 		{RXTX_REG41, 0xffff},  in xgene_phy_force_lat_summer_cal()
1355 		{RXTX_REG42, 0xffff},  in xgene_phy_force_lat_summer_cal()
1356 		{RXTX_REG43, 0xffff},  in xgene_phy_force_lat_summer_cal()
1357 		{RXTX_REG44, 0xffff},  in xgene_phy_force_lat_summer_cal()
1358 		{RXTX_REG45, 0xffff},  in xgene_phy_force_lat_summer_cal()
1359 		{RXTX_REG46, 0xffff},  in xgene_phy_force_lat_summer_cal()
1360 		{RXTX_REG47, 0xfffc},  in xgene_phy_force_lat_summer_cal()
1361 		{RXTX_REG48, 0x0},  in xgene_phy_force_lat_summer_cal()
1362 		{RXTX_REG49, 0x0},  in xgene_phy_force_lat_summer_cal()
1363 		{RXTX_REG50, 0x0},  in xgene_phy_force_lat_summer_cal()
1364 		{RXTX_REG51, 0x0},  in xgene_phy_force_lat_summer_cal()
1365 		{RXTX_REG52, 0x0},  in xgene_phy_force_lat_summer_cal()
1366 		{RXTX_REG53, 0x0},  in xgene_phy_force_lat_summer_cal()
1367 		{RXTX_REG54, 0x0},  in xgene_phy_force_lat_summer_cal()
1368 		{RXTX_REG55, 0x0},  in xgene_phy_force_lat_summer_cal()
1399 	serdes_wr(ctx, lane, RXTX_REG28, 0x7);  in xgene_phy_force_lat_summer_cal()
1400 	serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);  in xgene_phy_force_lat_summer_cal()
1405 	for (i = 0; i < ARRAY_SIZE(serdes_reg); i++)  in xgene_phy_force_lat_summer_cal()
1427 	int avg_loop = 0;  in xgene_phy_gen_avg_val()
1428 	int lat_do = 0, lat_xo = 0, lat_eo = 0, lat_so = 0;  in xgene_phy_gen_avg_val()
1429 	int lat_de = 0, lat_xe = 0, lat_ee = 0, lat_se = 0;  in xgene_phy_gen_avg_val()
1430 	int sum_cal = 0;  in xgene_phy_gen_avg_val()
1445 	serdes_wr(ctx, lane, RXTX_REG28, 0x0000);  in xgene_phy_gen_avg_val()
1447 	serdes_wr(ctx, lane, RXTX_REG31, 0x0000);  in xgene_phy_gen_avg_val()
1482 		if ((fail_even == 0 || fail_even == 1) &&  in xgene_phy_gen_avg_val()
1483 		    (fail_odd == 0 || fail_odd == 1)) {  in xgene_phy_gen_avg_val()
1495 			dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",  in xgene_phy_gen_avg_val()
1498 			dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",  in xgene_phy_gen_avg_val()
1501 			dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr);  in xgene_phy_gen_avg_val()
1547 	dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",  in xgene_phy_gen_avg_val()
1552 	dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",  in xgene_phy_gen_avg_val()
1557 	dev_dbg(ctx->dev, "SUM 0x%x\n",  in xgene_phy_gen_avg_val()
1561 	val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1);  in xgene_phy_gen_avg_val()
1566 	val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1);  in xgene_phy_gen_avg_val()
1572 	val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0);  in xgene_phy_gen_avg_val()
1575 	serdes_wr(ctx, lane, RXTX_REG28, 0x0007);  in xgene_phy_gen_avg_val()
1577 	serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);  in xgene_phy_gen_avg_val()
1601 	for (i = 0; i < MAX_LANE; i++)  in xgene_phy_hw_init()
1605 	return 0;  in xgene_phy_hw_init()
1618 	if (args->args_count <= 0)  in xgene_phy_xlate()
1620 	if (args->args[0] >= MODE_MAX)  in xgene_phy_xlate()
1623 	ctx->mode = args->args[0];  in xgene_phy_xlate()
1636 		for (i = 0; i < count; i++)  in xgene_phy_get_param()
1641 	for (i = 0; i < count; i++)  in xgene_phy_get_param()
1665 	ctx->sds_base = devm_platform_ioremap_resource(pdev, 0);  in xgene_phy_probe()
1689 	for (i = 0; i < MAX_LANE; i++)  in xgene_phy_probe()