Lines Matching defs:src
86 #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5) argument
95 #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ argument
97 #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ argument
100 #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ argument
103 #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ argument
110 #define CFG_IND_ADDR_SET(dst, src) \ argument
115 #define I_RESET_B_SET(dst, src) \ argument
117 #define I_PLL_FBDIV_SET(dst, src) \ argument
119 #define I_CUSTOMEROV_SET(dst, src) \ argument
121 #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30) argument
122 #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31) argument
127 #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \ argument
130 #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \ argument
133 #define CMU_REG1_PLL_CP_SET(dst, src) \ argument
135 #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \ argument
137 #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \ argument
140 #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \ argument
143 #define CMU_REG2_PLL_REFDIV_SET(dst, src) \ argument
145 #define CMU_REG2_PLL_LFRES_SET(dst, src) \ argument
147 #define CMU_REG2_PLL_FBDIV_SET(dst, src) \ argument
150 #define CMU_REG3_VCOVARSEL_SET(dst, src) \ argument
152 #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \ argument
154 #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \ argument
158 #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \ argument
160 #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \ argument
162 #define CMU_REG5_PLL_LFCAP_SET(dst, src) \ argument
166 #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \ argument
168 #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \ argument
171 #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14) argument
172 #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10) argument
183 #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \ argument
185 #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \ argument
187 #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \ argument
189 #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \ argument
191 #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \ argument
194 #define CMU_REG10_VREG_REFSEL_SET(dst, src) \ argument
198 #define CMU_REG12_STATE_DELAY9_SET(dst, src) \ argument
206 #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \ argument
208 #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \ argument
210 #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \ argument
213 #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \ argument
215 #define CMU_REG17_RESERVED_7_SET(dst, src) \ argument
227 #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \ argument
233 #define CMU_REG30_LOCK_COUNT_SET(dst, src) \ argument
235 #define CMU_REG30_PCIE_MODE_SET(dst, src) \ argument
240 #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \ argument
242 #define CMU_REG32_IREF_ADJ_SET(dst, src) \ argument
246 #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \ argument
248 #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \ argument
250 #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \ argument
252 #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \ argument
255 #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \ argument
258 #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \ argument
260 #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \ argument
262 #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \ argument
270 #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \ argument
272 #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \ argument
274 #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \ argument
277 #define RXTX_REG1_RXACVCM_SET(dst, src) \ argument
279 #define RXTX_REG1_CTLE_EQ_SET(dst, src) \ argument
281 #define RXTX_REG1_RXVREG1_SET(dst, src) \ argument
283 #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \ argument
286 #define RXTX_REG2_VTT_ENA_SET(dst, src) \ argument
288 #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \ argument
290 #define RXTX_REG2_VTT_SEL_SET(dst, src) \ argument
294 #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \ argument
296 #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \ argument
299 #define RXTX_REG5_TX_CN1_SET(dst, src) \ argument
301 #define RXTX_REG5_TX_CP1_SET(dst, src) \ argument
303 #define RXTX_REG5_TX_CN2_SET(dst, src) \ argument
306 #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \ argument
308 #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \ argument
310 #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \ argument
312 #define RXTX_REG6_TX_IDLE_SET(dst, src) \ argument
314 #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \ argument
319 #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \ argument
321 #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \ argument
324 #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \ argument
326 #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \ argument
328 #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \ argument
330 #define RXTX_REG8_SD_VREF_SET(dst, src) \ argument
332 #define RXTX_REG8_SD_DISABLE_SET(dst, src) \ argument
335 #define RXTX_REG7_RESETB_RXD_SET(dst, src) \ argument
337 #define RXTX_REG7_RESETB_RXA_SET(dst, src) \ argument
340 #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \ argument
343 #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \ argument
346 #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \ argument
348 #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \ argument
351 #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \ argument
355 #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \ argument
357 #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \ argument
360 #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \ argument
362 #define RXTX_REG26_BLWC_ENA_SET(dst, src) \ argument
365 #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
366 #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
367 #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src))) argument
369 #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
370 #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
371 #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src))) argument
373 #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
374 #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
376 #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
377 #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
382 #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \ argument
402 #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \ argument
404 #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \ argument
406 #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \ argument
408 #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \ argument
411 #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \ argument
414 #define RXTX_REG89_MU_TH7_SET(dst, src) \ argument
416 #define RXTX_REG89_MU_TH8_SET(dst, src) \ argument
418 #define RXTX_REG89_MU_TH9_SET(dst, src) \ argument
421 #define RXTX_REG96_MU_FREQ1_SET(dst, src) \ argument
423 #define RXTX_REG96_MU_FREQ2_SET(dst, src) \ argument
425 #define RXTX_REG96_MU_FREQ3_SET(dst, src) \ argument
428 #define RXTX_REG99_MU_PHASE1_SET(dst, src) \ argument
430 #define RXTX_REG99_MU_PHASE2_SET(dst, src) \ argument
432 #define RXTX_REG99_MU_PHASE3_SET(dst, src) \ argument
435 #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \ argument
439 #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1) argument
441 #define RXTX_REG125_PQ_REG_SET(dst, src) \ argument
443 #define RXTX_REG125_SIGN_PQ_SET(dst, src) \ argument
445 #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \ argument
447 #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \ argument
449 #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \ argument
454 #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \ argument
456 #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \ argument
458 #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \ argument
460 #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \ argument
462 #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \ argument
465 #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \ argument
467 #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \ argument
469 #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \ argument
472 #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \ argument
474 #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \ argument
477 #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \ argument
479 #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \ argument
482 #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \ argument
484 #define RXTX_REG145_RXES_ENA_SET(dst, src) \ argument
486 #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \ argument
488 #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \ argument