Lines Matching defs:x
35 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
37 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
41 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument
43 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument
47 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ argument
49 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\ argument
56 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ argument
58 #define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\ argument
62 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\ argument
64 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\ argument
68 #define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\ argument
70 #define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\ argument
74 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\ argument
76 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\ argument
80 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\ argument
82 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\ argument
89 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\ argument
91 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\ argument
98 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\ argument
100 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\ argument
107 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\ argument
109 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\ argument
113 #define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\ argument
115 #define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\ argument
119 #define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\ argument
121 #define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\ argument
125 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\ argument
127 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\ argument
131 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\ argument
133 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\ argument
137 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\ argument
139 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\ argument
146 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\ argument
148 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\ argument
152 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\ argument
154 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\ argument
158 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\ argument
160 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\ argument
164 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\ argument
166 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\ argument
170 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\ argument
172 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\ argument
179 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\ argument
181 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\ argument
185 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\ argument
187 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\ argument
191 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\ argument
193 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\ argument
197 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\ argument
199 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\ argument
203 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\ argument
205 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\ argument
209 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\ argument
211 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\ argument
215 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\ argument
217 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\ argument
221 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\ argument
223 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\ argument
230 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\ argument
232 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\ argument
236 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\ argument
238 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\ argument
245 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\ argument
247 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\ argument
251 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\ argument
253 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\ argument
257 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\ argument
259 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\ argument
263 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\ argument
265 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\ argument
272 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\ argument
274 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\ argument
281 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\ argument
283 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\ argument
287 #define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\ argument
289 #define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\ argument
293 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\ argument
295 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\ argument
302 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\ argument
304 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\ argument
311 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\ argument
313 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\ argument
320 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\ argument
322 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\ argument
329 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\ argument
331 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\ argument
335 #define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\ argument
337 #define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\ argument
341 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\ argument
343 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\ argument
347 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\ argument
349 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\ argument
353 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\ argument
355 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\ argument
362 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\ argument
364 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\ argument
371 #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\ argument
373 #define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\ argument
377 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\ argument
379 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\ argument
383 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\ argument
385 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\ argument
389 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\ argument
391 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\ argument
395 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\ argument
397 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\ argument
404 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\ argument
406 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\ argument
410 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\ argument
412 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\ argument
419 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\ argument
421 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\ argument
428 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\ argument
430 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\ argument
434 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\ argument
436 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\ argument
443 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\ argument
445 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\ argument
449 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\ argument
451 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\ argument
458 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\ argument
460 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\ argument
464 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\ argument
466 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\ argument
470 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\ argument
472 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\ argument
476 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\ argument
478 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\ argument
482 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\ argument
484 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\ argument
488 #define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\ argument
490 #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\ argument
497 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\ argument
499 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\ argument
503 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\ argument
505 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\ argument
512 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ argument
514 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ argument
518 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\ argument
520 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\ argument
527 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\ argument
529 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\ argument
533 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\ argument
535 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\ argument
542 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\ argument
544 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\ argument
548 #define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\ argument
550 #define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\ argument
554 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\ argument
556 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\ argument
560 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\ argument
562 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\ argument
566 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\ argument
568 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\ argument
575 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\ argument
577 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\ argument
581 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\ argument
583 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\ argument
587 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\ argument
589 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\ argument
593 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\ argument
595 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\ argument
602 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\ argument
604 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\ argument
608 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\ argument
610 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\ argument
617 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\ argument
619 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\ argument
623 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\ argument
625 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\ argument
632 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\ argument
634 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\ argument
638 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\ argument
640 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\ argument
647 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\ argument
649 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\ argument
656 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\ argument
658 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\ argument
665 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\ argument
667 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\ argument
671 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\ argument
673 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\ argument
680 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\ argument
682 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\ argument
686 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\ argument
688 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\ argument
692 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\ argument
694 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\ argument
701 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\ argument
703 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\ argument
707 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\ argument
709 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\ argument
713 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\ argument
715 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\ argument
719 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\ argument
721 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\ argument
725 #define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\ argument
727 #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\ argument
734 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\ argument
736 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\ argument
743 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\ argument
745 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\ argument
749 #define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\ argument
751 #define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\ argument
755 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\ argument
757 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\ argument
761 #define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\ argument
763 #define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\ argument
767 #define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\ argument
769 #define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\ argument
773 #define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\ argument
775 #define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\ argument
779 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\ argument
781 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\ argument
788 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\ argument
790 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\ argument
794 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
796 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
800 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\ argument
802 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\ argument
806 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\ argument
808 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\ argument
812 #define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\ argument
814 #define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\ argument
818 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\ argument
820 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\ argument
824 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\ argument
826 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\ argument
830 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\ argument
832 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\ argument
839 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\ argument
841 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\ argument
845 #define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\ argument
847 #define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\ argument
851 #define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\ argument
853 #define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\ argument
857 #define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\ argument
859 #define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\ argument
863 #define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\ argument
865 #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\ argument
872 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\ argument
874 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\ argument
878 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\ argument
880 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\ argument
884 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\ argument
886 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\ argument
893 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\ argument
895 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\ argument
899 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\ argument
901 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\ argument
905 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\ argument
907 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\ argument
911 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\ argument
913 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\ argument
917 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\ argument
919 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\ argument
926 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\ argument
928 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\ argument
935 #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\ argument
937 #define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\ argument
941 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument
943 #define SD10G_LANE_LANE_DF_LOL_GET(x)\ argument
947 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
949 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
953 #define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\ argument
955 #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\ argument
962 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\ argument
964 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\ argument
968 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\ argument
970 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\ argument
974 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\ argument
976 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\ argument
980 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\ argument
982 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\ argument
986 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\ argument
988 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\ argument
995 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\ argument
997 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\ argument
1001 #define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\ argument
1003 #define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\ argument
1007 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\ argument
1009 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\ argument
1013 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\ argument
1015 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\ argument
1019 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\ argument
1021 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\ argument
1025 #define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\ argument
1027 #define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\ argument
1031 #define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\ argument
1033 #define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\ argument
1037 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\ argument
1039 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\ argument
1046 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\ argument
1048 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\ argument
1052 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\ argument
1054 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\ argument
1058 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\ argument
1060 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\ argument
1064 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\ argument
1066 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\ argument
1070 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\ argument
1072 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\ argument
1079 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\ argument
1081 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\ argument
1085 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\ argument
1087 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\ argument
1091 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\ argument
1093 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\ argument
1097 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\ argument
1099 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\ argument
1103 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\ argument
1105 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\ argument
1112 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\ argument
1114 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\ argument
1118 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\ argument
1120 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\ argument
1127 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\ argument
1129 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\ argument
1133 #define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\ argument
1135 #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\ argument
1142 #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\ argument
1144 #define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\ argument
1148 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\ argument
1150 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\ argument
1154 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\ argument
1156 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\ argument
1160 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\ argument
1162 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\ argument
1169 #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\ argument
1171 #define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\ argument
1175 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\ argument
1177 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\ argument
1184 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\ argument
1186 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\ argument
1190 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
1192 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
1196 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\ argument
1198 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\ argument
1202 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\ argument
1204 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\ argument
1211 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\ argument
1213 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\ argument
1217 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\ argument
1219 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\ argument
1223 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\ argument
1225 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\ argument
1232 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\ argument
1234 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\ argument
1238 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\ argument
1240 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\ argument
1247 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\ argument
1249 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\ argument
1256 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\ argument
1258 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\ argument
1262 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\ argument
1264 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\ argument
1268 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\ argument
1270 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\ argument
1274 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\ argument
1276 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\ argument
1280 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\ argument
1282 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\ argument
1286 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\ argument
1288 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\ argument
1295 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\ argument
1297 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\ argument
1304 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\ argument
1306 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\ argument
1313 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\ argument
1315 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\ argument
1319 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\ argument
1321 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\ argument
1328 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\ argument
1330 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\ argument
1337 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\ argument
1339 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\ argument
1343 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\ argument
1345 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\ argument
1352 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ argument
1354 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ argument
1358 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\ argument
1360 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\ argument
1367 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\ argument
1369 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\ argument
1376 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\ argument
1378 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\ argument
1382 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\ argument
1384 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\ argument
1388 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\ argument
1390 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\ argument
1394 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\ argument
1396 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\ argument
1400 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\ argument
1402 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\ argument
1406 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\ argument
1408 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\ argument
1415 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\ argument
1417 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\ argument
1421 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\ argument
1423 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\ argument
1430 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\ argument
1432 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\ argument
1436 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\ argument
1438 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\ argument
1445 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\ argument
1447 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\ argument
1451 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\ argument
1453 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\ argument
1457 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\ argument
1459 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\ argument
1466 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\ argument
1468 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\ argument
1475 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\ argument
1477 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\ argument
1484 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\ argument
1486 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\ argument
1490 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\ argument
1492 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\ argument
1496 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\ argument
1498 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\ argument
1505 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
1507 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
1511 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\ argument
1513 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\ argument
1517 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\ argument
1519 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\ argument
1526 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\ argument
1528 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\ argument
1532 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\ argument
1534 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\ argument
1538 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\ argument
1540 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\ argument
1544 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\ argument
1546 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\ argument
1550 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\ argument
1552 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\ argument
1559 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\ argument
1561 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\ argument
1565 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\ argument
1567 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\ argument
1571 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\ argument
1573 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\ argument
1577 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\ argument
1579 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\ argument
1586 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\ argument
1588 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\ argument
1595 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\ argument
1597 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\ argument
1601 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\ argument
1603 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\ argument
1607 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\ argument
1609 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\ argument
1613 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\ argument
1615 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\ argument
1619 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\ argument
1621 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\ argument
1628 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\ argument
1630 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\ argument
1634 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\ argument
1636 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\ argument
1640 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\ argument
1642 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\ argument
1646 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\ argument
1648 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\ argument
1652 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\ argument
1654 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\ argument
1658 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\ argument
1660 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\ argument
1664 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\ argument
1666 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\ argument
1670 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\ argument
1672 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\ argument
1679 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\ argument
1681 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\ argument
1685 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\ argument
1687 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\ argument
1694 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\ argument
1696 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\ argument
1703 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\ argument
1705 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\ argument
1709 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\ argument
1711 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\ argument
1715 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\ argument
1717 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\ argument
1721 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\ argument
1723 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\ argument
1730 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\ argument
1732 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\ argument
1736 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\ argument
1738 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\ argument
1742 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\ argument
1744 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\ argument
1748 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\ argument
1750 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\ argument
1754 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\ argument
1756 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\ argument
1760 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\ argument
1762 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\ argument
1766 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\ argument
1768 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\ argument
1772 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\ argument
1774 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\ argument
1781 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\ argument
1783 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\ argument
1787 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\ argument
1789 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\ argument
1793 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\ argument
1795 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\ argument
1799 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\ argument
1801 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\ argument
1805 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\ argument
1807 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\ argument
1814 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\ argument
1816 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\ argument
1823 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\ argument
1825 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\ argument
1832 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\ argument
1834 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\ argument
1841 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\ argument
1843 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\ argument
1850 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\ argument
1852 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\ argument
1856 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\ argument
1858 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\ argument
1862 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\ argument
1864 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\ argument
1868 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\ argument
1870 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\ argument
1877 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\ argument
1879 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\ argument
1883 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\ argument
1885 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\ argument
1889 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\ argument
1891 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\ argument
1898 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\ argument
1900 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\ argument
1904 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\ argument
1906 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\ argument
1913 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\ argument
1915 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\ argument
1919 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\ argument
1921 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\ argument
1928 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\ argument
1930 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\ argument
1934 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\ argument
1936 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\ argument
1940 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\ argument
1942 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\ argument
1946 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\ argument
1948 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\ argument
1952 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\ argument
1954 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\ argument
1958 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\ argument
1960 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\ argument
1964 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\ argument
1966 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\ argument
1970 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\ argument
1972 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\ argument
1979 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\ argument
1981 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\ argument
1985 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\ argument
1987 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\ argument
1991 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\ argument
1993 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\ argument
1997 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\ argument
1999 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\ argument
2003 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\ argument
2005 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\ argument
2009 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\ argument
2011 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\ argument
2015 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\ argument
2017 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\ argument
2024 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\ argument
2026 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\ argument
2033 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\ argument
2035 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\ argument
2042 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\ argument
2044 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\ argument
2051 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\ argument
2053 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\ argument
2060 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\ argument
2062 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\ argument
2066 #define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\ argument
2068 #define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\ argument
2072 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
2074 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
2078 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\ argument
2080 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\ argument
2087 #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\ argument
2089 #define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\ argument
2093 #define SD6G_LANE_LANE_DF_LOL_SET(x)\ argument
2095 #define SD6G_LANE_LANE_DF_LOL_GET(x)\ argument
2099 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
2101 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
2105 #define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\ argument
2107 #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\ argument
2114 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\ argument
2116 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\ argument
2120 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\ argument
2122 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\ argument
2126 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\ argument
2128 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\ argument
2132 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\ argument
2134 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\ argument
2141 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\ argument
2143 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\ argument
2147 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\ argument
2149 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ argument
2157 #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\ argument
2159 #define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\ argument
2163 #define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\ argument
2165 #define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\ argument
2169 #define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\ argument
2171 #define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\ argument
2175 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\ argument
2177 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\ argument
2181 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\ argument
2183 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\ argument
2187 #define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\ argument
2189 #define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\ argument
2193 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\ argument
2195 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\ argument
2199 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\ argument
2201 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\ argument
2209 #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\ argument
2211 #define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\ argument
2215 #define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\ argument
2217 #define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\ argument
2221 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\ argument
2223 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\ argument
2227 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\ argument
2229 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\ argument
2233 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\ argument
2235 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\ argument
2242 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\ argument
2244 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\ argument
2248 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\ argument
2250 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\ argument
2254 #define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\ argument
2256 #define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\ argument
2260 #define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\ argument
2262 #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\ argument
2269 #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\ argument
2271 #define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\ argument
2275 #define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\ argument
2277 #define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\ argument
2281 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\ argument
2283 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\ argument
2287 #define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\ argument
2289 #define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\ argument
2293 #define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\ argument
2295 #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\ argument
2302 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\ argument
2304 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\ argument
2311 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\ argument
2313 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\ argument
2317 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\ argument
2319 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\ argument
2323 #define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\ argument
2325 #define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\ argument
2329 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\ argument
2331 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\ argument
2338 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\ argument
2340 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\ argument
2347 #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\ argument
2349 #define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\ argument
2353 #define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\ argument
2355 #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\ argument
2362 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\ argument
2364 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\ argument
2368 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
2370 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
2374 #define SD_CMU_CMU_45_RESERVED_SET(x)\ argument
2376 #define SD_CMU_CMU_45_RESERVED_GET(x)\ argument
2380 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\ argument
2382 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\ argument
2386 #define SD_CMU_CMU_45_RESERVED_2_SET(x)\ argument
2388 #define SD_CMU_CMU_45_RESERVED_2_GET(x)\ argument
2392 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\ argument
2394 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\ argument
2398 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\ argument
2400 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\ argument
2404 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\ argument
2406 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\ argument
2413 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\ argument
2415 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\ argument
2422 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\ argument
2424 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\ argument
2428 #define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\ argument
2430 #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\ argument
2437 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\ argument
2439 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\ argument
2443 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\ argument
2445 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\ argument
2452 #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\ argument
2454 #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\ argument
2461 #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\ argument
2463 #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\ argument
2470 #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\ argument
2472 #define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\ argument
2476 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ argument
2478 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ argument
2482 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\ argument
2484 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\ argument
2488 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\ argument
2490 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\ argument
2494 #define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\ argument
2496 #define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\ argument
2500 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\ argument
2502 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\ argument
2506 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\ argument
2508 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\ argument
2515 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ argument
2517 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ argument
2521 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\ argument
2523 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\ argument
2527 #define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\ argument
2529 #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ argument
2537 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\ argument
2539 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\ argument
2546 #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\ argument
2548 #define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\ argument
2552 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument
2554 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument
2558 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument
2560 #define SD_LANE_MISC_MUX_ENA_GET(x)\ argument
2564 #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\ argument
2566 #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\ argument
2573 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\ argument
2575 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\ argument
2579 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\ argument
2581 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\ argument
2588 #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\ argument
2590 #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\ argument
2597 #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\ argument
2599 #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\ argument
2606 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\ argument
2608 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\ argument
2612 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ argument
2614 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ argument
2618 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\ argument
2620 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\ argument
2624 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\ argument
2626 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\ argument
2630 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\ argument
2632 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\ argument
2636 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\ argument
2638 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\ argument
2642 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\ argument
2644 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\ argument
2648 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\ argument
2650 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\ argument
2654 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\ argument
2656 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\ argument
2660 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\ argument
2662 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\ argument
2666 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\ argument
2668 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\ argument
2672 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\ argument
2674 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\ argument
2678 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\ argument
2680 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\ argument
2684 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\ argument
2686 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\ argument
2690 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\ argument
2692 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\ argument
2696 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\ argument
2698 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\ argument
2705 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\ argument
2707 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\ argument
2711 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\ argument
2713 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\ argument
2717 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\ argument
2719 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\ argument
2723 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\ argument
2725 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\ argument
2729 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\ argument
2731 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\ argument
2735 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\ argument
2737 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\ argument
2741 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\ argument
2743 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\ argument
2747 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\ argument
2749 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\ argument
2753 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\ argument
2755 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\ argument
2759 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\ argument
2761 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\ argument
2765 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\ argument
2767 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\ argument
2774 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ argument
2776 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ argument
2780 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\ argument
2782 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\ argument
2786 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\ argument
2788 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ argument
2796 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\ argument
2798 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\ argument