1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk.h>
19 #include "phy-mtk-io.h"
79 #define XSP_REF_CLK		26	/* MHZ */
87 	struct clk *ref_clk;	/* reference clock of anolog phy */
105 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
112 	void __iomem *pbase = inst->port_base;  in u2_phy_slew_rate_calibrate()
118 	if (inst->eye_src)  in u2_phy_slew_rate_calibrate()
149 		tmp = xsphy->src_ref_clk * xsphy->src_coef;  in u2_phy_slew_rate_calibrate()
156 	dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in u2_phy_slew_rate_calibrate()
157 		inst->index, fm_out, calib_val,  in u2_phy_slew_rate_calibrate()
158 		xsphy->src_ref_clk, xsphy->src_coef);  in u2_phy_slew_rate_calibrate()
170 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_init()
181 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_power_on()
182 	u32 index = inst->index;  in u2_phy_instance_power_on()
190 	dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_on()
196 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_power_off()
197 	u32 index = inst->index;  in u2_phy_instance_power_off()
205 	dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_off()
214 	tmp = readl(inst->port_base + XSP_U2PHYDTM1);  in u2_phy_instance_set_mode()
229 	writel(tmp, inst->port_base + XSP_U2PHYDTM1);  in u2_phy_instance_set_mode()
235 	struct device *dev = &inst->phy->dev;  in phy_parse_property()
237 	switch (inst->type) {  in phy_parse_property()
239 		device_property_read_u32(dev, "mediatek,efuse-intr",  in phy_parse_property()
240 					 &inst->efuse_intr);  in phy_parse_property()
241 		device_property_read_u32(dev, "mediatek,eye-src",  in phy_parse_property()
242 					 &inst->eye_src);  in phy_parse_property()
243 		device_property_read_u32(dev, "mediatek,eye-vrt",  in phy_parse_property()
244 					 &inst->eye_vrt);  in phy_parse_property()
245 		device_property_read_u32(dev, "mediatek,eye-term",  in phy_parse_property()
246 					 &inst->eye_term);  in phy_parse_property()
247 		dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",  in phy_parse_property()
248 			inst->efuse_intr, inst->eye_src,  in phy_parse_property()
249 			inst->eye_vrt, inst->eye_term);  in phy_parse_property()
252 		device_property_read_u32(dev, "mediatek,efuse-intr",  in phy_parse_property()
253 					 &inst->efuse_intr);  in phy_parse_property()
254 		device_property_read_u32(dev, "mediatek,efuse-tx-imp",  in phy_parse_property()
255 					 &inst->efuse_tx_imp);  in phy_parse_property()
256 		device_property_read_u32(dev, "mediatek,efuse-rx-imp",  in phy_parse_property()
257 					 &inst->efuse_rx_imp);  in phy_parse_property()
258 		dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",  in phy_parse_property()
259 			inst->efuse_intr, inst->efuse_tx_imp,  in phy_parse_property()
260 			inst->efuse_rx_imp);  in phy_parse_property()
263 		dev_err(xsphy->dev, "incompatible phy type\n");  in phy_parse_property()
271 	void __iomem *pbase = inst->port_base;  in u2_phy_props_set()
273 	if (inst->efuse_intr)  in u2_phy_props_set()
275 				     inst->efuse_intr);  in u2_phy_props_set()
277 	if (inst->eye_src)  in u2_phy_props_set()
279 				     inst->eye_src);  in u2_phy_props_set()
281 	if (inst->eye_vrt)  in u2_phy_props_set()
283 				     inst->eye_vrt);  in u2_phy_props_set()
285 	if (inst->eye_term)  in u2_phy_props_set()
287 				     inst->eye_term);  in u2_phy_props_set()
293 	void __iomem *pbase = inst->port_base;  in u3_phy_props_set()
295 	if (inst->efuse_intr)  in u3_phy_props_set()
296 		mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00,  in u3_phy_props_set()
297 				     RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr);  in u3_phy_props_set()
299 	if (inst->efuse_tx_imp)  in u3_phy_props_set()
301 				     RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp);  in u3_phy_props_set()
303 	if (inst->efuse_rx_imp)  in u3_phy_props_set()
305 				     RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);  in u3_phy_props_set()
311 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_init()
314 	ret = clk_prepare_enable(inst->ref_clk);  in mtk_phy_init()
316 		dev_err(xsphy->dev, "failed to enable ref_clk\n");  in mtk_phy_init()
320 	switch (inst->type) {  in mtk_phy_init()
329 		dev_err(xsphy->dev, "incompatible phy type\n");  in mtk_phy_init()
330 		clk_disable_unprepare(inst->ref_clk);  in mtk_phy_init()
331 		return -EINVAL;  in mtk_phy_init()
340 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_on()
342 	if (inst->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
353 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_off()
355 	if (inst->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
365 	clk_disable_unprepare(inst->ref_clk);  in mtk_phy_exit()
372 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_set_mode()
374 	if (inst->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
385 	struct device_node *phy_np = args->np;  in mtk_phy_xlate()
388 	if (args->args_count != 1) {  in mtk_phy_xlate()
390 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
393 	for (index = 0; index < xsphy->nphys; index++)  in mtk_phy_xlate()
394 		if (phy_np == xsphy->phys[index]->phy->dev.of_node) {  in mtk_phy_xlate()
395 			inst = xsphy->phys[index];  in mtk_phy_xlate()
401 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
404 	inst->type = args->args[0];  in mtk_phy_xlate()
405 	if (!(inst->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
406 	      inst->type == PHY_TYPE_USB3)) {  in mtk_phy_xlate()
407 		dev_err(dev, "unsupported phy type: %d\n", inst->type);  in mtk_phy_xlate()
408 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
413 	return inst->phy;  in mtk_phy_xlate()
433 	struct device *dev = &pdev->dev;  in mtk_xsphy_probe()
434 	struct device_node *np = dev->of_node;  in mtk_xsphy_probe()
443 		return -ENOMEM;  in mtk_xsphy_probe()
445 	xsphy->nphys = of_get_child_count(np);  in mtk_xsphy_probe()
446 	xsphy->phys = devm_kcalloc(dev, xsphy->nphys,  in mtk_xsphy_probe()
447 				       sizeof(*xsphy->phys), GFP_KERNEL);  in mtk_xsphy_probe()
448 	if (!xsphy->phys)  in mtk_xsphy_probe()
449 		return -ENOMEM;  in mtk_xsphy_probe()
451 	xsphy->dev = dev;  in mtk_xsphy_probe()
458 		xsphy->glb_base = devm_ioremap_resource(dev, glb_res);  in mtk_xsphy_probe()
459 		if (IS_ERR(xsphy->glb_base)) {  in mtk_xsphy_probe()
461 			return PTR_ERR(xsphy->glb_base);  in mtk_xsphy_probe()
465 	xsphy->src_ref_clk = XSP_REF_CLK;  in mtk_xsphy_probe()
466 	xsphy->src_coef = XSP_SLEW_RATE_COEF;  in mtk_xsphy_probe()
468 	device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",  in mtk_xsphy_probe()
469 				 &xsphy->src_ref_clk);  in mtk_xsphy_probe()
470 	device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);  in mtk_xsphy_probe()
480 			return -ENOMEM;  in mtk_xsphy_probe()
482 		xsphy->phys[port] = inst;  in mtk_xsphy_probe()
492 			dev_err(dev, "failed to get address resource(id-%d)\n",  in mtk_xsphy_probe()
497 		inst->port_base = devm_ioremap_resource(&phy->dev, &res);  in mtk_xsphy_probe()
498 		if (IS_ERR(inst->port_base)) {  in mtk_xsphy_probe()
500 			return PTR_ERR(inst->port_base);  in mtk_xsphy_probe()
503 		inst->phy = phy;  in mtk_xsphy_probe()
504 		inst->index = port;  in mtk_xsphy_probe()
508 		inst->ref_clk = devm_clk_get(&phy->dev, "ref");  in mtk_xsphy_probe()
509 		if (IS_ERR(inst->ref_clk)) {  in mtk_xsphy_probe()
510 			dev_err(dev, "failed to get ref_clk(id-%d)\n", port);  in mtk_xsphy_probe()
511 			return PTR_ERR(inst->ref_clk);  in mtk_xsphy_probe()
522 		.name	= "mtk-xsphy",
530 MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");