Lines Matching +full:10 +full:base
3 * MediaTek 10GE SerDes XFI T-PHY driver
34 #define XTP_PCS_PWD_ASYNC_MASK GENMASK(11, 10)
61 * @base: IO memory area to access phy registers.
65 * @da_war: Enables work-around for 10GBase-R mode.
68 void __iomem *base; member
106 /* Is overriding 10GBase-R tuning value required? */ in mtk_xfi_tphy_setup()
110 * - USXGMII PCS (64b/66b coding) for 5G/10G in mtk_xfi_tphy_setup()
111 * - LynxI PCS (8b/10b coding) for 1G/2.5G in mtk_xfi_tphy_setup()
118 mtk_phy_update_bits(xfi_tphy->base + 0x9024, 0x100000, is_10g ? 0x0 : 0x100000); in mtk_xfi_tphy_setup()
119 mtk_phy_update_bits(xfi_tphy->base + 0x2020, 0x202000, is_5g ? 0x202000 : 0x0); in mtk_xfi_tphy_setup()
120 mtk_phy_update_bits(xfi_tphy->base + 0x2030, 0x500, is_1g ? 0x0 : 0x500); in mtk_xfi_tphy_setup()
121 mtk_phy_update_bits(xfi_tphy->base + 0x2034, 0xa00, is_1g ? 0x0 : 0xa00); in mtk_xfi_tphy_setup()
122 mtk_phy_update_bits(xfi_tphy->base + 0x2040, 0x340000, is_1g ? 0x200000 : 0x140000); in mtk_xfi_tphy_setup()
125 mtk_phy_update_bits(xfi_tphy->base + 0x50f0, 0xc10, is_1g ? 0x410 : is_5g ? 0x800 : 0x400); in mtk_xfi_tphy_setup()
126 mtk_phy_update_bits(xfi_tphy->base + 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000); in mtk_xfi_tphy_setup()
129 mtk_phy_update_bits(xfi_tphy->base + 0x506c, 0x30000, is_5g ? 0x0 : 0x30000); in mtk_xfi_tphy_setup()
130 mtk_phy_update_bits(xfi_tphy->base + 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000); in mtk_xfi_tphy_setup()
131 mtk_phy_update_bits(xfi_tphy->base + 0x5074, 0x180000, is_5g ? 0x180000 : 0x0); in mtk_xfi_tphy_setup()
132 mtk_phy_update_bits(xfi_tphy->base + 0x5078, 0xf000400, is_5g ? 0x8000000 : in mtk_xfi_tphy_setup()
134 mtk_phy_update_bits(xfi_tphy->base + 0x507c, 0x5000500, is_5g ? 0x4000400 : in mtk_xfi_tphy_setup()
136 mtk_phy_update_bits(xfi_tphy->base + 0x5080, 0x1410, is_1g ? 0x400 : is_5g ? 0x1010 : 0x0); in mtk_xfi_tphy_setup()
137 mtk_phy_update_bits(xfi_tphy->base + 0x5084, 0x30300, is_1g ? 0x30300 : in mtk_xfi_tphy_setup()
140 mtk_phy_update_bits(xfi_tphy->base + 0x5088, 0x60200, is_1g ? 0x20200 : in mtk_xfi_tphy_setup()
145 mtk_phy_update_bits(xfi_tphy->base + 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000); in mtk_xfi_tphy_setup()
146 mtk_phy_update_bits(xfi_tphy->base + 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000); in mtk_xfi_tphy_setup()
147 mtk_phy_update_bits(xfi_tphy->base + 0x50ec, 0xa00, is_1g ? 0x200 : 0x800); in mtk_xfi_tphy_setup()
148 mtk_phy_update_bits(xfi_tphy->base + 0x50a8, 0xee0000, is_5g ? 0x800000 : in mtk_xfi_tphy_setup()
150 mtk_phy_update_bits(xfi_tphy->base + 0x6004, 0x190000, is_5g ? 0x0 : 0x190000); in mtk_xfi_tphy_setup()
153 writel(0x01423342, xfi_tphy->base + 0x00f8); in mtk_xfi_tphy_setup()
155 writel(0x00a132a1, xfi_tphy->base + 0x00f8); in mtk_xfi_tphy_setup()
157 writel(0x009c329c, xfi_tphy->base + 0x00f8); in mtk_xfi_tphy_setup()
159 writel(0x00fa32fa, xfi_tphy->base + 0x00f8); in mtk_xfi_tphy_setup()
162 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_F4, in mtk_xfi_tphy_setup()
169 mtk_phy_set_bits(xfi_tphy->base + 0x0030, 0xc00); in mtk_xfi_tphy_setup()
173 xfi_tphy->base + REG_DIG_GLB_70); in mtk_xfi_tphy_setup()
176 writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40); in mtk_xfi_tphy_setup()
179 mtk_phy_update_bits(xfi_tphy->base + 0x30b0, 0x30, 0x20); in mtk_xfi_tphy_setup()
180 writel(0x00008a01, xfi_tphy->base + 0x3028); in mtk_xfi_tphy_setup()
181 writel(0x0000a884, xfi_tphy->base + 0x302c); in mtk_xfi_tphy_setup()
182 writel(0x00083002, xfi_tphy->base + 0x3024); in mtk_xfi_tphy_setup()
186 writel(0x00011110, xfi_tphy->base + 0x3010); in mtk_xfi_tphy_setup()
187 writel(0x40704000, xfi_tphy->base + 0x3048); in mtk_xfi_tphy_setup()
189 writel(0x00022220, xfi_tphy->base + 0x3010); in mtk_xfi_tphy_setup()
190 writel(0x0f020a01, xfi_tphy->base + 0x5064); in mtk_xfi_tphy_setup()
191 writel(0x06100600, xfi_tphy->base + 0x50b4); in mtk_xfi_tphy_setup()
193 writel(0x40704000, xfi_tphy->base + 0x3048); in mtk_xfi_tphy_setup()
195 writel(0x47684100, xfi_tphy->base + 0x3048); in mtk_xfi_tphy_setup()
199 writel(0x0000c000, xfi_tphy->base + 0x3064); in mtk_xfi_tphy_setup()
202 mtk_phy_update_bits(xfi_tphy->base + 0x3050, 0xa8000000, in mtk_xfi_tphy_setup()
204 mtk_phy_update_bits(xfi_tphy->base + 0x3054, 0xaa, in mtk_xfi_tphy_setup()
208 writel(0x00000f00, xfi_tphy->base + 0x306c); in mtk_xfi_tphy_setup()
210 writel(0x22000f00, xfi_tphy->base + 0x306c); in mtk_xfi_tphy_setup()
212 writel(0x20200f00, xfi_tphy->base + 0x306c); in mtk_xfi_tphy_setup()
214 mtk_phy_update_bits(xfi_tphy->base + 0xa008, 0x10000, da_war ? 0x10000 : 0x0); in mtk_xfi_tphy_setup()
216 mtk_phy_update_bits(xfi_tphy->base + 0xa060, 0x50000, use_lynxi_pcs ? 0x50000 : 0x40000); in mtk_xfi_tphy_setup()
219 mtk_phy_update_bits(xfi_tphy->base + REG_ANA_GLB_D0, in mtk_xfi_tphy_setup()
225 mtk_phy_set_bits(xfi_tphy->base + REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN); in mtk_xfi_tphy_setup()
228 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_GLB_70, in mtk_xfi_tphy_setup()
233 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, in mtk_xfi_tphy_setup()
244 mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT); in mtk_xfi_tphy_setup()
249 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, in mtk_xfi_tphy_setup()
254 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, in mtk_xfi_tphy_setup()
260 mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT); in mtk_xfi_tphy_setup()
265 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN); in mtk_xfi_tphy_setup()
266 mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN); in mtk_xfi_tphy_setup()
269 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_40, in mtk_xfi_tphy_setup()
326 usleep_range(1, 10); in mtk_xfi_tphy_reset()
380 * whether the DA work-around for 10GBase-R is required from Device Tree and
406 xfi_tphy->base = devm_platform_ioremap_resource(pdev, 0); in mtk_xfi_tphy_probe()
407 if (IS_ERR(xfi_tphy->base)) in mtk_xfi_tphy_probe()
408 return PTR_ERR(xfi_tphy->base); in mtk_xfi_tphy_probe()
448 MODULE_DESCRIPTION("MediaTek 10GE SerDes XFI T-PHY driver");