1 // SPDX-License-Identifier: GPL-2.0
3  * MediaTek MIPI CSI v0.5 driver
9 #include <dt-bindings/phy/phy.h>
19 #include "phy-mtk-io.h"
20 #include "phy-mtk-mipi-csi-0-5-rx-reg.h"
29 	u32 mode;  member
76 	void __iomem *base = port->base;  in mtk_mipi_phy_power_on()
79 	 * The driver currently supports DPHY and CD-PHY phys,  in mtk_mipi_phy_power_on()
80 	 * but the only mode supported is DPHY,  in mtk_mipi_phy_power_on()
81 	 * so CD-PHY capable phys must be configured in DPHY mode  in mtk_mipi_phy_power_on()
83 	if (port->type == CDPHY) {  in mtk_mipi_phy_power_on()
94 	 * CSIXA_LNR0 --> D2  in mtk_mipi_phy_power_on()
95 	 * CSIXA_LNR1 --> D0  in mtk_mipi_phy_power_on()
96 	 * CSIXA_LNR2 --> C  in mtk_mipi_phy_power_on()
97 	 * CSIXB_LNR0 --> D1  in mtk_mipi_phy_power_on()
98 	 * CSIXB_LNR1 --> D3  in mtk_mipi_phy_power_on()
130 	if (port->type == CDPHY)  in mtk_mipi_phy_power_on()
155 	void __iomem *base = port->base;  in mtk_mipi_phy_power_off()
157 	/* Disable MIPI BG. */  in mtk_mipi_phy_power_off()
173 	 * If PHY is CD-PHY then we need to get the operating mode  in mtk_mipi_cdphy_xlate()
174 	 * For now only D-PHY mode is supported  in mtk_mipi_cdphy_xlate()
176 	if (priv->type == CDPHY) {  in mtk_mipi_cdphy_xlate()
177 		if (args->args_count != 1) {  in mtk_mipi_cdphy_xlate()
179 			return ERR_PTR(-EINVAL);  in mtk_mipi_cdphy_xlate()
181 		switch (args->args[0]) {  in mtk_mipi_cdphy_xlate()
183 			priv->mode = DPHY;  in mtk_mipi_cdphy_xlate()
184 			if (priv->num_lanes != 4) {  in mtk_mipi_cdphy_xlate()
185 				dev_err(dev, "Only 4D1C mode is supported for now!\n");  in mtk_mipi_cdphy_xlate()
186 				return ERR_PTR(-EINVAL);  in mtk_mipi_cdphy_xlate()
190 			dev_err(dev, "Unsupported PHY type: %i\n", args->args[0]);  in mtk_mipi_cdphy_xlate()
191 			return ERR_PTR(-EINVAL);  in mtk_mipi_cdphy_xlate()
194 		if (args->args_count) {  in mtk_mipi_cdphy_xlate()
196 			return ERR_PTR(-EINVAL);  in mtk_mipi_cdphy_xlate()
198 		priv->mode = DPHY;  in mtk_mipi_cdphy_xlate()
201 	return priv->phy;  in mtk_mipi_cdphy_xlate()
212 	struct device *dev = &pdev->dev;  in mtk_mipi_cdphy_probe()
221 		return -ENOMEM;  in mtk_mipi_cdphy_probe()
225 	port->dev = dev;  in mtk_mipi_cdphy_probe()
227 	port->base = devm_platform_ioremap_resource(pdev, 0);  in mtk_mipi_cdphy_probe()
228 	if (IS_ERR(port->base))  in mtk_mipi_cdphy_probe()
229 		return PTR_ERR(port->base);  in mtk_mipi_cdphy_probe()
231 	ret = of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes);  in mtk_mipi_cdphy_probe()
233 		dev_err(dev, "Failed to read num-lanes property: %i\n", ret);  in mtk_mipi_cdphy_probe()
238 	 * phy-type is optional, if not present, PHY is considered to be CD-PHY  in mtk_mipi_cdphy_probe()
240 	if (device_property_present(dev, "phy-type")) {  in mtk_mipi_cdphy_probe()
241 		ret = of_property_read_u32(dev->of_node, "phy-type", &phy_type);  in mtk_mipi_cdphy_probe()
243 			dev_err(dev, "Failed to read phy-type property: %i\n", ret);  in mtk_mipi_cdphy_probe()
248 			port->type = DPHY;  in mtk_mipi_cdphy_probe()
252 			return -EINVAL;  in mtk_mipi_cdphy_probe()
255 		port->type = CDPHY;  in mtk_mipi_cdphy_probe()
264 	port->phy = phy;  in mtk_mipi_cdphy_probe()
278 	{ .compatible = "mediatek,mt8365-csi-rx" },
286 		.name	= "mtk-mipi-csi-0-5",
292 MODULE_DESCRIPTION("MediaTek MIPI CSI CD-PHY v0.5 Driver");