Lines Matching full:base
26 void __iomem *base; member
39 static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base) in mtk_phy_csi_cdphy_ana_eq_tune() argument
41 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
42 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
43 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
44 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
45 mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
46 mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
48 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
49 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
50 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
51 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
52 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
53 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
56 static void mtk_phy_csi_dphy_ana_eq_tune(void __iomem *base) in mtk_phy_csi_dphy_ana_eq_tune() argument
58 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
59 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
60 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
61 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
62 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
63 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
65 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
66 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
67 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
68 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
69 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
70 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
76 void __iomem *base = port->base; in mtk_mipi_phy_power_on() local
84 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSI0A_CPHY_EN, 0); in mtk_mipi_phy_power_on()
85 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
100 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKMODE_EN, 0); in mtk_mipi_phy_power_on()
101 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKSEL, 1); in mtk_mipi_phy_power_on()
102 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKMODE_EN, 0); in mtk_mipi_phy_power_on()
103 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKSEL, 1); in mtk_mipi_phy_power_on()
104 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKMODE_EN, 1); in mtk_mipi_phy_power_on()
105 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKSEL, 1); in mtk_mipi_phy_power_on()
107 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
109 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKSEL, 1); in mtk_mipi_phy_power_on()
110 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
112 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKSEL, 1); in mtk_mipi_phy_power_on()
113 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
115 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKSEL, 1); in mtk_mipi_phy_power_on()
118 mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1); in mtk_mipi_phy_power_on()
119 mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1); in mtk_mipi_phy_power_on()
120 mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1); in mtk_mipi_phy_power_on()
122 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, in mtk_mipi_phy_power_on()
124 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, in mtk_mipi_phy_power_on()
126 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, in mtk_mipi_phy_power_on()
131 mtk_phy_csi_cdphy_ana_eq_tune(base); in mtk_mipi_phy_power_on()
133 mtk_phy_csi_dphy_ana_eq_tune(base); in mtk_mipi_phy_power_on()
136 mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90); in mtk_mipi_phy_power_on()
138 mtk_phy_update_field(base + MIPI_RX_ANA24_CSIXA, RG_CSIXA_RESERVE, 0x40); in mtk_mipi_phy_power_on()
139 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA24_CSIXA, RG_CSIXA_RESERVE, 0x40); in mtk_mipi_phy_power_on()
140 mtk_phy_update_field(base + MIPI_RX_WRAPPER80_CSIXA, CSR_CSI_RST_MODE, 0); in mtk_mipi_phy_power_on()
141 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_WRAPPER80_CSIXA, CSR_CSI_RST_MODE, 0); in mtk_mipi_phy_power_on()
143 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 1); in mtk_mipi_phy_power_on()
144 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 1); in mtk_mipi_phy_power_on()
146 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 1); in mtk_mipi_phy_power_on()
147 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 1); in mtk_mipi_phy_power_on()
155 void __iomem *base = port->base; in mtk_mipi_phy_power_off() local
158 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 0); in mtk_mipi_phy_power_off()
159 mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 0); in mtk_mipi_phy_power_off()
161 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 0); in mtk_mipi_phy_power_off()
162 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 0); in mtk_mipi_phy_power_off()
227 port->base = devm_platform_ioremap_resource(pdev, 0); in mtk_mipi_cdphy_probe()
228 if (IS_ERR(port->base)) in mtk_mipi_cdphy_probe()
229 return PTR_ERR(port->base); in mtk_mipi_cdphy_probe()