Lines Matching +full:4 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
77 #define PLL_READY_TX_BIT BIT(4)
110 #define CLK100M_125M_EN BIT(4)
130 #define PRD_TXSWING_MASK BIT(4)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
162 #define BUNDLE_SAMPLE_CTRL BIT(4)
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
222 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
256 /* lane 2 */
300 /* 0 1 2 3 4 5 6 7 */
301 /*-----------------------------------------------------------*/
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
397 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_set() argument
400 if (lane->id == 2) { in comphy_lane_reg_set()
401 /* lane 2 PHY registers are accessed indirectly */ in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
406 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
407 lane->priv->lane1_phy_regs : in comphy_lane_reg_set()
408 lane->priv->lane0_phy_regs; in comphy_lane_reg_set()
415 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_poll() argument
421 if (lane->id == 2) { in comphy_lane_reg_poll()
424 /* lane 2 PHY registers are accessed indirectly */ in comphy_lane_reg_poll()
426 lane->priv->lane2_phy_indirect + in comphy_lane_reg_poll()
429 ret = readl_poll_timeout(lane->priv->lane2_phy_indirect + in comphy_lane_reg_poll()
434 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_poll()
435 lane->priv->lane1_phy_regs : in comphy_lane_reg_poll()
436 lane->priv->lane0_phy_regs; in comphy_lane_reg_poll()
447 static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane, in comphy_periph_reg_set() argument
450 comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg), in comphy_periph_reg_set()
454 static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane, in comphy_periph_reg_poll() argument
460 return readl_poll_timeout(lane->priv->comphy_regs + in comphy_periph_reg_poll()
461 COMPHY_PHY_REG(lane->id, reg), in comphy_periph_reg_poll()
468 mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_set_phy_selector() argument
473 switch (lane->mode) { in mvebu_a3700_comphy_set_phy_selector()
476 if (lane->id == 2) in mvebu_a3700_comphy_set_phy_selector()
483 if (lane->id == 0) in mvebu_a3700_comphy_set_phy_selector()
485 else if (lane->id == 1) in mvebu_a3700_comphy_set_phy_selector()
492 if (lane->id == 2) in mvebu_a3700_comphy_set_phy_selector()
494 else if (lane->id == 0) in mvebu_a3700_comphy_set_phy_selector()
502 if (lane->id == 1) in mvebu_a3700_comphy_set_phy_selector()
512 spin_lock_irqsave(&lane->priv->lock, flags); in mvebu_a3700_comphy_set_phy_selector()
514 old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); in mvebu_a3700_comphy_set_phy_selector()
516 writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); in mvebu_a3700_comphy_set_phy_selector()
518 spin_unlock_irqrestore(&lane->priv->lock, flags); in mvebu_a3700_comphy_set_phy_selector()
520 dev_dbg(lane->dev, in mvebu_a3700_comphy_set_phy_selector()
521 "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n", in mvebu_a3700_comphy_set_phy_selector()
522 lane->id, lane->mode, old, new); in mvebu_a3700_comphy_set_phy_selector()
526 dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id, in mvebu_a3700_comphy_set_phy_selector()
527 lane->mode); in mvebu_a3700_comphy_set_phy_selector()
528 return -EINVAL; in mvebu_a3700_comphy_set_phy_selector()
532 mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_sata_power_on() argument
538 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_sata_power_on()
543 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, in mvebu_a3700_comphy_sata_power_on()
548 if (lane->invert_tx) in mvebu_a3700_comphy_sata_power_on()
550 if (lane->invert_rx) in mvebu_a3700_comphy_sata_power_on()
553 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_sata_power_on()
555 /* 1. Select 40-bit data width */ in mvebu_a3700_comphy_sata_power_on()
556 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, in mvebu_a3700_comphy_sata_power_on()
560 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_sata_power_on()
567 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_sata_power_on()
570 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, in mvebu_a3700_comphy_sata_power_on()
573 /* 4. Reset reserved bit */ in mvebu_a3700_comphy_sata_power_on()
574 comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG, in mvebu_a3700_comphy_sata_power_on()
577 /* 5. Set vendor-specific configuration (It is done in sata driver) */ in mvebu_a3700_comphy_sata_power_on()
578 /* XXX: in U-Boot below sequence was executed in this place, in Linux in mvebu_a3700_comphy_sata_power_on()
579 * not. Now it is done only in U-Boot before this comphy in mvebu_a3700_comphy_sata_power_on()
580 * initialization - tests shows that it works ok, but in case of any in mvebu_a3700_comphy_sata_power_on()
590 ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, in mvebu_a3700_comphy_sata_power_on()
594 dev_err(lane->dev, "Failed to lock SATA PLL\n"); in mvebu_a3700_comphy_sata_power_on()
599 static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, in comphy_gbe_phy_init() argument
624 comphy_lane_reg_set(lane, addr, val, 0xFFFF); in comphy_gbe_phy_init()
629 mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_ethernet_power_on() argument
635 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_ethernet_power_on()
648 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
650 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ in mvebu_a3700_comphy_ethernet_power_on()
653 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
659 switch (lane->submode) { in mvebu_a3700_comphy_ethernet_power_on()
666 /* 2500Base-X, SerDes speed 3.125G */ in mvebu_a3700_comphy_ethernet_power_on()
671 dev_err(lane->dev, in mvebu_a3700_comphy_ethernet_power_on()
672 "unsupported phy speed %d on comphy lane%d\n", in mvebu_a3700_comphy_ethernet_power_on()
673 lane->submode, lane->id); in mvebu_a3700_comphy_ethernet_power_on()
674 return -EINVAL; in mvebu_a3700_comphy_ethernet_power_on()
678 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
689 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
697 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
703 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_ethernet_power_on()
709 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
725 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
739 * the related GEN table during real chip bring-up. We only required to in mvebu_a3700_comphy_ethernet_power_on()
744 dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n", in mvebu_a3700_comphy_ethernet_power_on()
745 lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G"); in mvebu_a3700_comphy_ethernet_power_on()
746 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_ethernet_power_on()
747 comphy_gbe_phy_init(lane, in mvebu_a3700_comphy_ethernet_power_on()
748 lane->submode != PHY_INTERFACE_MODE_2500BASEX); in mvebu_a3700_comphy_ethernet_power_on()
754 if (lane->invert_tx) in mvebu_a3700_comphy_ethernet_power_on()
756 if (lane->invert_rx) in mvebu_a3700_comphy_ethernet_power_on()
759 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
769 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
775 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, in mvebu_a3700_comphy_ethernet_power_on()
780 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", in mvebu_a3700_comphy_ethernet_power_on()
781 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
788 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); in mvebu_a3700_comphy_ethernet_power_on()
797 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, in mvebu_a3700_comphy_ethernet_power_on()
800 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, in mvebu_a3700_comphy_ethernet_power_on()
805 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", in mvebu_a3700_comphy_ethernet_power_on()
806 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
810 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, in mvebu_a3700_comphy_ethernet_power_on()
814 dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", in mvebu_a3700_comphy_ethernet_power_on()
815 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
821 mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_usb3_power_on() argument
827 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_usb3_power_on()
832 comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); in mvebu_a3700_comphy_usb3_power_on()
835 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The in mvebu_a3700_comphy_usb3_power_on()
840 * 1. Set PRD_TXDEEMPH (3.5db de-emph) in mvebu_a3700_comphy_usb3_power_on()
845 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask); in mvebu_a3700_comphy_usb3_power_on()
849 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency in mvebu_a3700_comphy_usb3_power_on()
851 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db in mvebu_a3700_comphy_usb3_power_on()
857 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask); in mvebu_a3700_comphy_usb3_power_on()
862 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4, in mvebu_a3700_comphy_usb3_power_on()
866 * 4. Set Override Margining Controls From the MAC: in mvebu_a3700_comphy_usb3_power_on()
867 * Use margining signals from lane configuration in mvebu_a3700_comphy_usb3_power_on()
869 comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL, in mvebu_a3700_comphy_usb3_power_on()
873 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles in mvebu_a3700_comphy_usb3_power_on()
879 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask); in mvebu_a3700_comphy_usb3_power_on()
882 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K in mvebu_a3700_comphy_usb3_power_on()
884 comphy_lane_reg_set(lane, COMPHY_GEN2_SET2, in mvebu_a3700_comphy_usb3_power_on()
894 comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask); in mvebu_a3700_comphy_usb3_power_on()
900 if (lane->priv->xtal_is_40m) { in mvebu_a3700_comphy_usb3_power_on()
913 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_usb3_power_on()
918 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); in mvebu_a3700_comphy_usb3_power_on()
923 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, in mvebu_a3700_comphy_usb3_power_on()
929 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN); in mvebu_a3700_comphy_usb3_power_on()
932 * 11. Set 20-bit data width in mvebu_a3700_comphy_usb3_power_on()
934 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, in mvebu_a3700_comphy_usb3_power_on()
942 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask); in mvebu_a3700_comphy_usb3_power_on()
948 if (lane->invert_tx) in mvebu_a3700_comphy_usb3_power_on()
950 if (lane->invert_rx) in mvebu_a3700_comphy_usb3_power_on()
953 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_usb3_power_on()
958 comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN, in mvebu_a3700_comphy_usb3_power_on()
964 comphy_lane_reg_set(lane, COMPHY_GEN2_SET3, in mvebu_a3700_comphy_usb3_power_on()
972 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); in mvebu_a3700_comphy_usb3_power_on()
977 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, in mvebu_a3700_comphy_usb3_power_on()
980 dev_err(lane->dev, "Failed to lock USB3 PLL\n"); in mvebu_a3700_comphy_usb3_power_on()
986 mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_pcie_power_on() argument
992 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_pcie_power_on()
997 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, in mvebu_a3700_comphy_pcie_power_on()
1001 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, in mvebu_a3700_comphy_pcie_power_on()
1005 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1, in mvebu_a3700_comphy_pcie_power_on()
1008 /* 4. Change RX wait */ in mvebu_a3700_comphy_pcie_power_on()
1012 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1015 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, in mvebu_a3700_comphy_pcie_power_on()
1021 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1025 * PCI-E driver in mvebu_a3700_comphy_pcie_power_on()
1033 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_pcie_power_on()
1041 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1044 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, in mvebu_a3700_comphy_pcie_power_on()
1050 if (lane->invert_tx) in mvebu_a3700_comphy_pcie_power_on()
1052 if (lane->invert_rx) in mvebu_a3700_comphy_pcie_power_on()
1055 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1060 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1065 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, in mvebu_a3700_comphy_pcie_power_on()
1068 dev_err(lane->dev, "Failed to lock PCIE PLL\n"); in mvebu_a3700_comphy_pcie_power_on()
1074 mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_sata_power_off() argument
1077 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, in mvebu_a3700_comphy_sata_power_off()
1081 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, in mvebu_a3700_comphy_sata_power_off()
1086 mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_ethernet_power_off() argument
1093 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_off()
1097 mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_pcie_power_off() argument
1100 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, in mvebu_a3700_comphy_pcie_power_off()
1104 static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_usb3_power_off() argument
1112 static bool mvebu_a3700_comphy_check_mode(int lane, in mvebu_a3700_comphy_check_mode() argument
1123 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_check_mode()
1138 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_set_mode() local
1140 if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) { in mvebu_a3700_comphy_set_mode()
1141 dev_err(lane->dev, "invalid COMPHY mode\n"); in mvebu_a3700_comphy_set_mode()
1142 return -EINVAL; in mvebu_a3700_comphy_set_mode()
1146 if (phy->power_count && in mvebu_a3700_comphy_set_mode()
1147 (lane->mode != mode || lane->submode != submode)) in mvebu_a3700_comphy_set_mode()
1148 return -EBUSY; in mvebu_a3700_comphy_set_mode()
1150 /* Just remember the mode, ->power_on() will do the real setup */ in mvebu_a3700_comphy_set_mode()
1151 lane->mode = mode; in mvebu_a3700_comphy_set_mode()
1152 lane->submode = submode; in mvebu_a3700_comphy_set_mode()
1159 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_power_on() local
1161 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, in mvebu_a3700_comphy_power_on()
1162 lane->submode)) { in mvebu_a3700_comphy_power_on()
1163 dev_err(lane->dev, "invalid COMPHY mode\n"); in mvebu_a3700_comphy_power_on()
1164 return -EINVAL; in mvebu_a3700_comphy_power_on()
1167 switch (lane->mode) { in mvebu_a3700_comphy_power_on()
1169 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1170 return mvebu_a3700_comphy_usb3_power_on(lane); in mvebu_a3700_comphy_power_on()
1172 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1173 return mvebu_a3700_comphy_sata_power_on(lane); in mvebu_a3700_comphy_power_on()
1175 dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1176 return mvebu_a3700_comphy_ethernet_power_on(lane); in mvebu_a3700_comphy_power_on()
1178 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1179 return mvebu_a3700_comphy_pcie_power_on(lane); in mvebu_a3700_comphy_power_on()
1181 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); in mvebu_a3700_comphy_power_on()
1182 return -EOPNOTSUPP; in mvebu_a3700_comphy_power_on()
1188 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_power_off() local
1190 switch (lane->id) { in mvebu_a3700_comphy_power_off()
1192 mvebu_a3700_comphy_usb3_power_off(lane); in mvebu_a3700_comphy_power_off()
1193 mvebu_a3700_comphy_ethernet_power_off(lane); in mvebu_a3700_comphy_power_off()
1196 mvebu_a3700_comphy_pcie_power_off(lane); in mvebu_a3700_comphy_power_off()
1197 mvebu_a3700_comphy_ethernet_power_off(lane); in mvebu_a3700_comphy_power_off()
1200 mvebu_a3700_comphy_usb3_power_off(lane); in mvebu_a3700_comphy_power_off()
1201 mvebu_a3700_comphy_sata_power_off(lane); in mvebu_a3700_comphy_power_off()
1204 dev_err(lane->dev, "invalid COMPHY mode\n"); in mvebu_a3700_comphy_power_off()
1205 return -EINVAL; in mvebu_a3700_comphy_power_off()
1219 struct mvebu_a3700_comphy_lane *lane; in mvebu_a3700_comphy_xlate() local
1227 lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_xlate()
1229 port = args->args[0]; in mvebu_a3700_comphy_xlate()
1230 if (port != 0 && (port != 1 || lane->id != 0)) { in mvebu_a3700_comphy_xlate()
1231 dev_err(lane->dev, "invalid port number %u\n", port); in mvebu_a3700_comphy_xlate()
1232 return ERR_PTR(-EINVAL); in mvebu_a3700_comphy_xlate()
1235 lane->invert_tx = args->args[1] & BIT(0); in mvebu_a3700_comphy_xlate()
1236 lane->invert_rx = args->args[1] & BIT(1); in mvebu_a3700_comphy_xlate()
1250 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in mvebu_a3700_comphy_probe()
1252 return -ENOMEM; in mvebu_a3700_comphy_probe()
1254 spin_lock_init(&priv->lock); in mvebu_a3700_comphy_probe()
1257 priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1258 if (IS_ERR(priv->comphy_regs)) in mvebu_a3700_comphy_probe()
1259 return PTR_ERR(priv->comphy_regs); in mvebu_a3700_comphy_probe()
1263 priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1264 if (IS_ERR(priv->lane1_phy_regs)) in mvebu_a3700_comphy_probe()
1265 return PTR_ERR(priv->lane1_phy_regs); in mvebu_a3700_comphy_probe()
1269 priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1270 if (IS_ERR(priv->lane0_phy_regs)) in mvebu_a3700_comphy_probe()
1271 return PTR_ERR(priv->lane0_phy_regs); in mvebu_a3700_comphy_probe()
1275 priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1276 if (IS_ERR(priv->lane2_phy_indirect)) in mvebu_a3700_comphy_probe()
1277 return PTR_ERR(priv->lane2_phy_indirect); in mvebu_a3700_comphy_probe()
1284 clk = clk_get(&pdev->dev, "xtal"); in mvebu_a3700_comphy_probe()
1286 if (PTR_ERR(clk) == -EPROBE_DEFER) in mvebu_a3700_comphy_probe()
1287 return -EPROBE_DEFER; in mvebu_a3700_comphy_probe()
1288 dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n", in mvebu_a3700_comphy_probe()
1293 dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n", in mvebu_a3700_comphy_probe()
1297 priv->xtal_is_40m = true; in mvebu_a3700_comphy_probe()
1303 dev_set_drvdata(&pdev->dev, priv); in mvebu_a3700_comphy_probe()
1305 for_each_available_child_of_node(pdev->dev.of_node, child) { in mvebu_a3700_comphy_probe()
1306 struct mvebu_a3700_comphy_lane *lane; in mvebu_a3700_comphy_probe() local
1313 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", in mvebu_a3700_comphy_probe()
1319 dev_err(&pdev->dev, "invalid 'reg' property\n"); in mvebu_a3700_comphy_probe()
1323 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); in mvebu_a3700_comphy_probe()
1324 if (!lane) { in mvebu_a3700_comphy_probe()
1326 return -ENOMEM; in mvebu_a3700_comphy_probe()
1329 phy = devm_phy_create(&pdev->dev, child, in mvebu_a3700_comphy_probe()
1336 lane->priv = priv; in mvebu_a3700_comphy_probe()
1337 lane->dev = &pdev->dev; in mvebu_a3700_comphy_probe()
1338 lane->mode = PHY_MODE_INVALID; in mvebu_a3700_comphy_probe()
1339 lane->submode = PHY_INTERFACE_MODE_NA; in mvebu_a3700_comphy_probe()
1340 lane->id = lane_id; in mvebu_a3700_comphy_probe()
1341 lane->invert_tx = false; in mvebu_a3700_comphy_probe()
1342 lane->invert_rx = false; in mvebu_a3700_comphy_probe()
1343 phy_set_drvdata(phy, lane); in mvebu_a3700_comphy_probe()
1352 provider = devm_of_phy_provider_register(&pdev->dev, in mvebu_a3700_comphy_probe()
1359 { .compatible = "marvell,comphy-a3700" },
1367 .name = "mvebu-a3700-comphy",