17 #define HOST_VSA_ADDR		0x0
18 #define HOST_VSA_DATA		0x4
19 #define PORT_SCR_CTL		0x2c
20 #define PORT_VSR_ADDR		0x78
21 #define PORT_VSR_DATA		0x7c
23 #define CONTROL_REGISTER	0x0
24 #define MBUS_SIZE_CONTROL	0x4
31 #define BG2_PHY_BASE		0x080
32 #define BG2Q_PHY_BASE		0x200
34 /* register 0x01 */
35 #define REF_FREF_SEL_25		BIT(0)
36 #define PHY_BERLIN_MODE_SATA	(0x0 << 5)
38 /* register 0x02 */
41 /* register 0x23 */
42 #define DATA_BIT_WIDTH_10	(0x0 << 10)
43 #define DATA_BIT_WIDTH_20	(0x1 << 10)
44 #define DATA_BIT_WIDTH_40	(0x2 << 10)
46 /* register 0x25 */
47 #define PHY_GEN_MAX_1_5		(0x0 << 10)
48 #define PHY_GEN_MAX_3_0		(0x1 << 10)
49 #define PHY_GEN_MAX_6_0		(0x2 << 10)
85 	void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);  in phy_berlin_sata_power_on()
105 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,  in phy_berlin_sata_power_on()
106 				    0x00ff,  in phy_berlin_sata_power_on()
110 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,  in phy_berlin_sata_power_on()
111 				    0x0c00, PHY_GEN_MAX_6_0);  in phy_berlin_sata_power_on()
114 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,  in phy_berlin_sata_power_on()
115 				    0x0c00, DATA_BIT_WIDTH_40);  in phy_berlin_sata_power_on()
118 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,  in phy_berlin_sata_power_on()
119 				    0x0000, USE_MAX_PLL_RATE);  in phy_berlin_sata_power_on()
124 	regval |= 0x30;  in phy_berlin_sata_power_on()
131 	return 0;  in phy_berlin_sata_power_on()
154 	return 0;  in phy_berlin_sata_power_off()
163 	if (WARN_ON(args->args[0] >= priv->nphys))  in phy_berlin_sata_phy_xlate()
166 	for (i = 0; i < priv->nphys; i++) {  in phy_berlin_sata_phy_xlate()
167 		if (priv->phys[i]->index == args->args[0])  in phy_berlin_sata_phy_xlate()
196 	int ret, i = 0;  in phy_berlin_sata_probe()
203 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in phy_berlin_sata_probe()
216 	if (priv->nphys == 0)  in phy_berlin_sata_probe()