59 	unsigned int mhz;  in keembay_emmc_phy_power()  local
84 	mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000);  in keembay_emmc_phy_power()
85 	if (mhz <= 200 && mhz >= 170)  in keembay_emmc_phy_power()
87 	else if (mhz <= 170 && mhz >= 140)  in keembay_emmc_phy_power()
89 	else if (mhz <= 140 && mhz >= 110)  in keembay_emmc_phy_power()
91 	else if (mhz <= 110 && mhz >= 80)  in keembay_emmc_phy_power()
93 	else if (mhz <= 80 && mhz >= 50)  in keembay_emmc_phy_power()
99 	if (mhz > 175)  in keembay_emmc_phy_power()
100 		dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);  in keembay_emmc_phy_power()
125 				       0, 50);  in keembay_emmc_phy_power()
156 	if (mhz == 0)  in keembay_emmc_phy_power()
161 	 * our source clock is at 50 MHz and that lock time scales linearly  in keembay_emmc_phy_power()
171 	 * generous and give it 50ms.  in keembay_emmc_phy_power()
175 				       0, 50 * USEC_PER_MSEC);  in keembay_emmc_phy_power()