Lines Matching +full:hi970 +full:- +full:pcie +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe phy driver for Kirin 970
25 #include <linux/phy/phy.h>
32 /* PCIe CTRL registers */
44 /* PCIe PHY registers */
168 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val, in hi3670_apb_phy_writel() argument
171 writel(val, phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_writel()
174 static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg) in hi3670_apb_phy_readl() argument
176 return readl(phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_readl()
179 static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy, in hi3670_apb_phy_updatel() argument
184 regval = hi3670_apb_phy_readl(phy, reg); in hi3670_apb_phy_updatel()
187 hi3670_apb_phy_writel(phy, regval, reg); in hi3670_apb_phy_updatel()
190 static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy, in kirin_apb_natural_phy_writel() argument
193 writel(val, phy->base + reg); in kirin_apb_natural_phy_writel()
196 static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy, in kirin_apb_natural_phy_readl() argument
199 return readl(phy->base + reg); in kirin_apb_natural_phy_readl()
202 static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable) in hi3670_pcie_phy_oe_enable() argument
206 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); in hi3670_pcie_phy_oe_enable()
212 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); in hi3670_pcie_phy_oe_enable()
215 static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy) in hi3670_pcie_get_eyeparam() argument
217 struct device *dev = phy->dev; in hi3670_pcie_get_eyeparam()
221 np = dev->of_node; in hi3670_pcie_get_eyeparam()
223 ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param", in hi3670_pcie_get_eyeparam()
224 phy->eye_param, NUM_EYEPARAM); in hi3670_pcie_get_eyeparam()
230 phy->eye_param[i] = EYEPARAM_NOCFG; in hi3670_pcie_get_eyeparam()
233 static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy) in hi3670_pcie_set_eyeparam() argument
237 val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1); in hi3670_pcie_set_eyeparam()
239 if (phy->eye_param[1] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
241 val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]); in hi3670_pcie_set_eyeparam()
244 kirin_apb_natural_phy_writel(phy, val, in hi3670_pcie_set_eyeparam()
247 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2); in hi3670_pcie_set_eyeparam()
249 if (phy->eye_param[2] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
250 val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]); in hi3670_pcie_set_eyeparam()
254 if (phy->eye_param[3] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
255 val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]); in hi3670_pcie_set_eyeparam()
259 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2); in hi3670_pcie_set_eyeparam()
261 val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN); in hi3670_pcie_set_eyeparam()
262 if (phy->eye_param[0] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
264 val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]); in hi3670_pcie_set_eyeparam()
267 kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN); in hi3670_pcie_set_eyeparam()
269 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1); in hi3670_pcie_set_eyeparam()
270 if (phy->eye_param[4] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
272 val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]); in hi3670_pcie_set_eyeparam()
275 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1); in hi3670_pcie_set_eyeparam()
278 static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy) in hi3670_pcie_natural_cfg() argument
283 regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR, in hi3670_pcie_natural_cfg()
286 regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val); in hi3670_pcie_natural_cfg()
288 regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val); in hi3670_pcie_natural_cfg()
291 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val); in hi3670_pcie_natural_cfg()
294 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val); in hi3670_pcie_natural_cfg()
297 hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT, in hi3670_pcie_natural_cfg()
302 hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL, in hi3670_pcie_natural_cfg()
306 static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy) in hi3670_pcie_pll_init() argument
308 hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL, in hi3670_pcie_pll_init()
311 hi3670_apb_phy_updatel(phy, in hi3670_pcie_pll_init()
316 hi3670_apb_phy_updatel(phy, in hi3670_pcie_pll_init()
320 hi3670_apb_phy_updatel(phy, in hi3670_pcie_pll_init()
330 hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL, in hi3670_pcie_pll_init()
334 static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable) in hi3670_pcie_pll_ctrl() argument
336 struct device *dev = phy->dev; in hi3670_pcie_pll_ctrl()
342 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE, in hi3670_pcie_pll_ctrl()
346 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0); in hi3670_pcie_pll_ctrl()
350 return -EINVAL; in hi3670_pcie_pll_ctrl()
352 time--; in hi3670_pcie_pll_ctrl()
354 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0); in hi3670_pcie_pll_ctrl()
357 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP, in hi3670_pcie_pll_ctrl()
361 hi3670_apb_phy_updatel(phy, in hi3670_pcie_pll_ctrl()
366 hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP, in hi3670_pcie_pll_ctrl()
374 static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open) in hi3670_pcie_hp_debounce_gt() argument
378 regmap_write(phy->crgctrl, CRGPERIPH_PEREN12, in hi3670_pcie_hp_debounce_gt()
382 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, in hi3670_pcie_hp_debounce_gt()
386 static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open) in hi3670_pcie_phyref_gt() argument
390 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_phyref_gt()
397 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_phyref_gt()
400 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE); in hi3670_pcie_phyref_gt()
403 static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag) in hi3670_pcie_oe_ctrl() argument
407 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_oe_ctrl()
426 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_oe_ctrl()
429 static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open) in hi3670_pcie_ioref_gt() argument
434 regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR, in hi3670_pcie_ioref_gt()
437 hi3670_pcie_oe_ctrl(phy, true); in hi3670_pcie_ioref_gt()
440 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_ioref_gt()
442 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_ioref_gt()
445 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, in hi3670_pcie_ioref_gt()
450 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_ioref_gt()
452 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_ioref_gt()
455 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, in hi3670_pcie_ioref_gt()
458 hi3670_pcie_oe_ctrl(phy, false); in hi3670_pcie_ioref_gt()
462 static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on) in hi3670_pcie_allclk_ctrl() argument
464 struct device *dev = phy->dev; in hi3670_pcie_allclk_ctrl()
471 hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE, in hi3670_pcie_allclk_ctrl()
474 hi3670_pcie_pll_init(phy); in hi3670_pcie_allclk_ctrl()
476 ret = hi3670_pcie_pll_ctrl(phy, true); in hi3670_pcie_allclk_ctrl()
479 return -EINVAL; in hi3670_pcie_allclk_ctrl()
481 hi3670_pcie_hp_debounce_gt(phy, true); in hi3670_pcie_allclk_ctrl()
482 hi3670_pcie_phyref_gt(phy, true); in hi3670_pcie_allclk_ctrl()
483 hi3670_pcie_ioref_gt(phy, true); in hi3670_pcie_allclk_ctrl()
485 ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ); in hi3670_pcie_allclk_ctrl()
494 hi3670_pcie_ioref_gt(phy, false); in hi3670_pcie_allclk_ctrl()
495 hi3670_pcie_phyref_gt(phy, false); in hi3670_pcie_allclk_ctrl()
496 hi3670_pcie_hp_debounce_gt(phy, false); in hi3670_pcie_allclk_ctrl()
498 hi3670_pcie_pll_ctrl(phy, false); in hi3670_pcie_allclk_ctrl()
503 static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy) in is_pipe_clk_stable() argument
505 struct device *dev = phy->dev; in is_pipe_clk_stable()
510 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR); in is_pipe_clk_stable()
517 time--; in is_pipe_clk_stable()
518 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR); in is_pipe_clk_stable()
524 static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) in hi3670_pcie_noc_power() argument
526 struct device *dev = phy->dev; in hi3670_pcie_noc_power()
537 regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val); in hi3670_pcie_noc_power()
540 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val); in hi3670_pcie_noc_power()
544 dev_err(dev, "Failed to reverse noc power-status\n"); in hi3670_pcie_noc_power()
545 return -EINVAL; in hi3670_pcie_noc_power()
547 time--; in hi3670_pcie_noc_power()
548 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val); in hi3670_pcie_noc_power()
554 static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy) in hi3670_pcie_get_resources_from_pcie() argument
557 struct device *dev = phy->dev; in hi3670_pcie_get_resources_from_pcie()
560 pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie"); in hi3670_pcie_get_resources_from_pcie()
562 dev_err(dev, "no pcie node found in %s\n", in hi3670_pcie_get_resources_from_pcie()
563 dev->parent->of_node->full_name); in hi3670_pcie_get_resources_from_pcie()
564 return -ENODEV; in hi3670_pcie_get_resources_from_pcie()
569 dev_err(dev, "Didn't find pcie device\n"); in hi3670_pcie_get_resources_from_pcie()
570 return -ENODEV; in hi3670_pcie_get_resources_from_pcie()
575 * pcie-kirin currently registers directly just one regmap (although in hi3670_pcie_get_resources_from_pcie()
581 phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb"); in hi3670_pcie_get_resources_from_pcie()
582 if (!phy->apb) { in hi3670_pcie_get_resources_from_pcie()
584 return -ENODEV; in hi3670_pcie_get_resources_from_pcie()
590 static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable) in kirin_pcie_clk_ctrl() argument
597 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); in kirin_pcie_clk_ctrl()
601 ret = clk_prepare_enable(phy->phy_ref_clk); in kirin_pcie_clk_ctrl()
605 ret = clk_prepare_enable(phy->apb_sys_clk); in kirin_pcie_clk_ctrl()
609 ret = clk_prepare_enable(phy->apb_phy_clk); in kirin_pcie_clk_ctrl()
613 ret = clk_prepare_enable(phy->aclk); in kirin_pcie_clk_ctrl()
617 ret = clk_prepare_enable(phy->aux_clk); in kirin_pcie_clk_ctrl()
624 clk_disable_unprepare(phy->aux_clk); in kirin_pcie_clk_ctrl()
626 clk_disable_unprepare(phy->aclk); in kirin_pcie_clk_ctrl()
628 clk_disable_unprepare(phy->apb_phy_clk); in kirin_pcie_clk_ctrl()
630 clk_disable_unprepare(phy->apb_sys_clk); in kirin_pcie_clk_ctrl()
632 clk_disable_unprepare(phy->phy_ref_clk); in kirin_pcie_clk_ctrl()
637 static int hi3670_pcie_phy_init(struct phy *generic_phy) in hi3670_pcie_phy_init()
639 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy); in hi3670_pcie_phy_init() local
644 * access the reset-gpios and the APB registers, both from the in hi3670_pcie_phy_init()
645 * pcie-kirin driver. in hi3670_pcie_phy_init()
647 * The APB is obtained via the pcie driver's regmap in hi3670_pcie_phy_init()
648 * Such kind of resource can only be obtained during the PCIe in hi3670_pcie_phy_init()
649 * power_on sequence, as the code inside pcie-kirin needs to in hi3670_pcie_phy_init()
653 ret = hi3670_pcie_get_resources_from_pcie(phy); in hi3670_pcie_phy_init()
660 static int hi3670_pcie_phy_power_on(struct phy *generic_phy) in hi3670_pcie_phy_power_on()
662 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy); in hi3670_pcie_phy_power_on() local
666 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); in hi3670_pcie_phy_power_on()
669 hi3670_pcie_phy_oe_enable(phy, true); in hi3670_pcie_phy_power_on()
671 ret = kirin_pcie_clk_ctrl(phy, true); in hi3670_pcie_phy_power_on()
675 /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ in hi3670_pcie_phy_power_on()
676 regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); in hi3670_pcie_phy_power_on()
677 regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET, in hi3670_pcie_phy_power_on()
679 regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET, in hi3670_pcie_phy_power_on()
682 hi3670_pcie_natural_cfg(phy); in hi3670_pcie_phy_power_on()
684 ret = hi3670_pcie_allclk_ctrl(phy, true); in hi3670_pcie_phy_power_on()
689 hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN, in hi3670_pcie_phy_power_on()
693 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val); in hi3670_pcie_phy_power_on()
695 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val); in hi3670_pcie_phy_power_on()
698 ret = is_pipe_clk_stable(phy); in hi3670_pcie_phy_power_on()
702 hi3670_pcie_set_eyeparam(phy); in hi3670_pcie_phy_power_on()
704 ret = hi3670_pcie_noc_power(phy, false); in hi3670_pcie_phy_power_on()
711 kirin_pcie_clk_ctrl(phy, false); in hi3670_pcie_phy_power_on()
715 static int hi3670_pcie_phy_power_off(struct phy *generic_phy) in hi3670_pcie_phy_power_off()
717 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy); in hi3670_pcie_phy_power_off() local
719 hi3670_pcie_phy_oe_enable(phy, false); in hi3670_pcie_phy_power_off()
721 hi3670_pcie_allclk_ctrl(phy, false); in hi3670_pcie_phy_power_off()
724 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0); in hi3670_pcie_phy_power_off()
728 * kirin_pcie_clk_ctrl(phy, false); in hi3670_pcie_phy_power_off()
730 * CLK_IS_CRITICAL at clk-hi3670 driver, as powering such clocks off in hi3670_pcie_phy_power_off()
732 * While clk-hi3670 is not fixed, we cannot risk disabling clocks here. in hi3670_pcie_phy_power_off()
745 static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy, in hi3670_pcie_phy_get_resources() argument
748 struct device *dev = &pdev->dev; in hi3670_pcie_phy_get_resources()
751 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); in hi3670_pcie_phy_get_resources()
752 if (IS_ERR(phy->crgctrl)) in hi3670_pcie_phy_get_resources()
753 return PTR_ERR(phy->crgctrl); in hi3670_pcie_phy_get_resources()
755 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl"); in hi3670_pcie_phy_get_resources()
756 if (IS_ERR(phy->sysctrl)) in hi3670_pcie_phy_get_resources()
757 return PTR_ERR(phy->sysctrl); in hi3670_pcie_phy_get_resources()
759 phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl"); in hi3670_pcie_phy_get_resources()
760 if (IS_ERR(phy->pmctrl)) in hi3670_pcie_phy_get_resources()
761 return PTR_ERR(phy->pmctrl); in hi3670_pcie_phy_get_resources()
764 phy->phy_ref_clk = devm_clk_get(dev, "phy_ref"); in hi3670_pcie_phy_get_resources()
765 if (IS_ERR(phy->phy_ref_clk)) in hi3670_pcie_phy_get_resources()
766 return PTR_ERR(phy->phy_ref_clk); in hi3670_pcie_phy_get_resources()
768 phy->aux_clk = devm_clk_get(dev, "aux"); in hi3670_pcie_phy_get_resources()
769 if (IS_ERR(phy->aux_clk)) in hi3670_pcie_phy_get_resources()
770 return PTR_ERR(phy->aux_clk); in hi3670_pcie_phy_get_resources()
772 phy->apb_phy_clk = devm_clk_get(dev, "apb_phy"); in hi3670_pcie_phy_get_resources()
773 if (IS_ERR(phy->apb_phy_clk)) in hi3670_pcie_phy_get_resources()
774 return PTR_ERR(phy->apb_phy_clk); in hi3670_pcie_phy_get_resources()
776 phy->apb_sys_clk = devm_clk_get(dev, "apb_sys"); in hi3670_pcie_phy_get_resources()
777 if (IS_ERR(phy->apb_sys_clk)) in hi3670_pcie_phy_get_resources()
778 return PTR_ERR(phy->apb_sys_clk); in hi3670_pcie_phy_get_resources()
780 phy->aclk = devm_clk_get(dev, "aclk"); in hi3670_pcie_phy_get_resources()
781 if (IS_ERR(phy->aclk)) in hi3670_pcie_phy_get_resources()
782 return PTR_ERR(phy->aclk); in hi3670_pcie_phy_get_resources()
785 phy->base = devm_platform_ioremap_resource(pdev, 0); in hi3670_pcie_phy_get_resources()
786 if (IS_ERR(phy->base)) in hi3670_pcie_phy_get_resources()
787 return PTR_ERR(phy->base); in hi3670_pcie_phy_get_resources()
789 hi3670_pcie_get_eyeparam(phy); in hi3670_pcie_phy_get_resources()
797 struct device *dev = &pdev->dev; in hi3670_pcie_phy_probe()
798 struct hi3670_pcie_phy *phy; in hi3670_pcie_phy_probe() local
799 struct phy *generic_phy; in hi3670_pcie_phy_probe()
802 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in hi3670_pcie_phy_probe()
803 if (!phy) in hi3670_pcie_phy_probe()
804 return -ENOMEM; in hi3670_pcie_phy_probe()
806 phy->dev = dev; in hi3670_pcie_phy_probe()
808 ret = hi3670_pcie_phy_get_resources(phy, pdev); in hi3670_pcie_phy_probe()
812 generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops); in hi3670_pcie_phy_probe()
814 dev_err(dev, "failed to create PHY\n"); in hi3670_pcie_phy_probe()
818 phy_set_drvdata(generic_phy, phy); in hi3670_pcie_phy_probe()
826 .compatible = "hisilicon,hi970-pcie-phy",
842 MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");