15 #define LYNX_28G_PCC8				0x10a0
16 #define LYNX_28G_PCC8_SGMII			0x1
17 #define LYNX_28G_PCC8_SGMII_DIS			0x0
19 #define LYNX_28G_PCCC				0x10b0
20 #define LYNX_28G_PCCC_10GBASER			0x9
21 #define LYNX_28G_PCCC_USXGMII			0x1
22 #define LYNX_28G_PCCC_SXGMII_DIS		0x0
27 #define LYNX_28G_PLLnRSTCTL(pll)		(0x400 + (pll) * 0x100 + 0x0)
31 #define LYNX_28G_PLLnCR0(pll)			(0x400 + (pll) * 0x100 + 0x4)
33 #define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ	0x0
34 #define LYNX_28G_PLLnCR0_REFCLK_SEL_125MHZ	0x10000
35 #define LYNX_28G_PLLnCR0_REFCLK_SEL_156MHZ	0x20000
36 #define LYNX_28G_PLLnCR0_REFCLK_SEL_150MHZ	0x30000
37 #define LYNX_28G_PLLnCR0_REFCLK_SEL_161MHZ	0x40000
39 #define LYNX_28G_PLLnCR1(pll)			(0x400 + (pll) * 0x100 + 0x8)
41 #define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO	0x0
42 #define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO	0x10000000
43 #define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO	0x6000000
47 #define LYNX_28G_LNaGCR0(lane)			(0x800 + (lane) * 0x100 + 0x0)
49 #define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII	0x8
50 #define LYNX_28G_LNaGCR0_PROTO_SEL_XFI		0x50
51 #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK		GENMASK(2, 0)
52 #define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT	0x0
53 #define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT	0x2
56 #define LYNX_28G_LNaTRSTCTL(lane)		(0x800 + (lane) * 0x100 + 0x20)
62 #define LYNX_28G_LNaTGCR0(lane)			(0x800 + (lane) * 0x100 + 0x24)
63 #define LYNX_28G_LNaTGCR0_USE_PLLF		0x0
66 #define LYNX_28G_LNaTGCR0_N_RATE_FULL		0x0
67 #define LYNX_28G_LNaTGCR0_N_RATE_HALF		0x1000000
68 #define LYNX_28G_LNaTGCR0_N_RATE_QUARTER	0x2000000
71 #define LYNX_28G_LNaTECR0(lane)			(0x800 + (lane) * 0x100 + 0x30)
74 #define LYNX_28G_LNaRRSTCTL(lane)		(0x800 + (lane) * 0x100 + 0x40)
81 #define LYNX_28G_LNaRGCR0(lane)			(0x800 + (lane) * 0x100 + 0x44)
82 #define LYNX_28G_LNaRGCR0_USE_PLLF		0x0
86 #define LYNX_28G_LNaRGCR0_N_RATE_FULL		0x0
87 #define LYNX_28G_LNaRGCR0_N_RATE_HALF		0x1000000
88 #define LYNX_28G_LNaRGCR0_N_RATE_QUARTER	0x2000000
91 #define LYNX_28G_LNaRGCR1(lane)			(0x800 + (lane) * 0x100 + 0x48)
93 #define LYNX_28G_LNaRECR0(lane)			(0x800 + (lane) * 0x100 + 0x50)
94 #define LYNX_28G_LNaRECR1(lane)			(0x800 + (lane) * 0x100 + 0x54)
95 #define LYNX_28G_LNaRECR2(lane)			(0x800 + (lane) * 0x100 + 0x58)
97 #define LYNX_28G_LNaRSCCR0(lane)		(0x800 + (lane) * 0x100 + 0x74)
99 #define LYNX_28G_LNaPSS(lane)			(0x1000 + (lane) * 0x4)
101 #define LYNX_28G_LNaPSS_TYPE_SGMII		0x4
102 #define LYNX_28G_LNaPSS_TYPE_XFI		0x28
104 #define LYNX_28G_SGMIIaCR1(lane)		(0x1804 + (lane) * 0x10)
106 #define LYNX_28G_SGMIIaCR1_SGPCS_DIS		0x0
164 	for (i = 0; i < LYNX_28G_NUM_PLL; i++) {  in lynx_28g_supports_interface()
181 	for (i = 0; i < LYNX_28G_NUM_PLL; i++) {  in lynx_28g_pll_get()
230 	if (pll->id == 0) {  in lynx_28g_lane_set_pll()
249 			     GENMASK(3, 0) << lane_offset);  in lynx_28g_cleanup_lane()
255 			     GENMASK(3, 0) << lane_offset);  in lynx_28g_cleanup_lane()
273 		     GENMASK(3, 0) << lane_offset);  in lynx_28g_lane_set_sgmii()
290 	iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));  in lynx_28g_lane_set_sgmii()
291 	iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));  in lynx_28g_lane_set_sgmii()
292 	iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));  in lynx_28g_lane_set_sgmii()
293 	iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));  in lynx_28g_lane_set_sgmii()
294 	iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));  in lynx_28g_lane_set_sgmii()
295 	iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));  in lynx_28g_lane_set_sgmii()
309 		     GENMASK(3, 0) << lane_offset);  in lynx_28g_lane_set_10gbaser()
326 	iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));  in lynx_28g_lane_set_10gbaser()
327 	iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));  in lynx_28g_lane_set_10gbaser()
328 	iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));  in lynx_28g_lane_set_10gbaser()
329 	iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));  in lynx_28g_lane_set_10gbaser()
330 	iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));  in lynx_28g_lane_set_10gbaser()
331 	iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));  in lynx_28g_lane_set_10gbaser()
340 		return 0;  in lynx_28g_power_off()
355 	return 0;  in lynx_28g_power_off()
364 		return 0;  in lynx_28g_power_on()
379 	return 0;  in lynx_28g_power_on()
387 	int err = 0;  in lynx_28g_set_mode()
443 	return 0;  in lynx_28g_validate()
460 	return 0;  in lynx_28g_init()
477 	for (i = 0; i < LYNX_28G_NUM_PLL; i++) {  in lynx_28g_pll_read_configuration()
516 	for (i = 0; i < LYNX_28G_NUM_LANE; i++) {  in lynx_28g_cdr_lock_check()
562 	int idx = args->args[0];  in lynx_28g_xlate()
582 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in lynx_28g_probe()
588 	for (i = 0; i < LYNX_28G_NUM_LANE; i++) {  in lynx_28g_probe()
592 		memset(lane, 0, sizeof(*lane));  in lynx_28g_probe()