Lines Matching refs:ctrl_off
74 u32 ctrl_off; member
128 lane->ctrl_off = 0; in imx_hsio_init()
139 lane->ctrl_off = 0; in imx_hsio_init()
146 lane->ctrl_off = SZ_64K; in imx_hsio_init()
166 lane->ctrl_off = SZ_128K; in imx_hsio_init()
203 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
205 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
207 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
209 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
211 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
213 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
235 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_phy_resets()
237 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_phy_resets()
241 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N); in imx_hsio_sata_phy_resets()
243 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_phy_resets()
245 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N); in imx_hsio_sata_phy_resets()
306 addr = lane->ctrl_off + HSIO_PCIE_STS0; in imx_hsio_pcie_power_on()
325 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_power_on()
327 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_power_on()
403 lane->ctrl_off + HSIO_CTRL2, in imx_hsio_power_off()
406 lane->ctrl_off + HSIO_CTRL2, in imx_hsio_power_off()
409 lane->ctrl_off + HSIO_CTRL2, in imx_hsio_power_off()
413 lane->ctrl_off + HSIO_CTRL0, in imx_hsio_power_off()
416 lane->ctrl_off + HSIO_CTRL0, in imx_hsio_power_off()
419 lane->ctrl_off + HSIO_CTRL0, in imx_hsio_power_off()
475 regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_set_mode()
486 regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_set_speed()