Lines Matching +full:0 +full:x4124
19 #define USB3_PHY_OFFSET 0x0
20 #define USB2_PHY_OFFSET 0x38000
22 #define PHY_PMA_CMN_CTRL1 0xC800
23 #define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
24 #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
25 #define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
26 #define TB_ADDR_CMN_PLL0_INTDIV 0x0094
27 #define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
28 #define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
29 #define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
30 #define TB_ADDR_CMN_PLL0_SS_CTRL2 0x0099
31 #define TB_ADDR_CMN_PLL0_DSM_DIAG 0x0097
32 #define TB_ADDR_CMN_DIAG_PLL0_OVRD 0x01c2
33 #define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD 0x01c0
34 #define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD 0x01c1
35 #define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE 0x01C5
36 #define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE 0x01C6
37 #define TB_ADDR_CMN_DIAG_PLL0_LF_PROG 0x01C7
38 #define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE 0x01c4
39 #define TB_ADDR_CMN_PSM_CLK_CTRL 0x0061
40 #define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR 0x40ea
41 #define TB_ADDR_XCVR_PSM_RCTRL 0x4001
42 #define TB_ADDR_TX_PSC_A0 0x4100
43 #define TB_ADDR_TX_PSC_A1 0x4101
44 #define TB_ADDR_TX_PSC_A2 0x4102
45 #define TB_ADDR_TX_PSC_A3 0x4103
46 #define TB_ADDR_TX_DIAG_ECTRL_OVRD 0x41f5
47 #define TB_ADDR_TX_PSC_CAL 0x4106
48 #define TB_ADDR_TX_PSC_RDY 0x4107
49 #define TB_ADDR_RX_PSC_A0 0x8000
50 #define TB_ADDR_RX_PSC_A1 0x8001
51 #define TB_ADDR_RX_PSC_A2 0x8002
52 #define TB_ADDR_RX_PSC_A3 0x8003
53 #define TB_ADDR_RX_PSC_CAL 0x8006
54 #define TB_ADDR_RX_PSC_RDY 0x8007
55 #define TB_ADDR_TX_TXCC_MGNLS_MULT_000 0x4058
56 #define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
57 #define TB_ADDR_RX_SLC_CU_ITER_TMR 0x80e3
58 #define TB_ADDR_RX_SIGDET_HL_FILT_TMR 0x8090
59 #define TB_ADDR_RX_SAMP_DAC_CTRL 0x8058
60 #define TB_ADDR_RX_DIAG_SIGDET_TUNE 0x81dc
61 #define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 0x81df
62 #define TB_ADDR_RX_DIAG_BS_TM 0x81f5
63 #define TB_ADDR_RX_DIAG_DFE_CTRL1 0x81d3
64 #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 0x81c7
65 #define TB_ADDR_RX_DIAG_ILL_E_TRIM0 0x81c2
66 #define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 0x81c1
67 #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 0x81c9
68 #define TB_ADDR_RX_DIAG_RXFE_TM3 0x81f8
69 #define TB_ADDR_RX_DIAG_RXFE_TM4 0x81f9
70 #define TB_ADDR_RX_DIAG_LFPSDET_TUNE 0x81dd
71 #define TB_ADDR_RX_DIAG_DFE_CTRL3 0x81d5
72 #define TB_ADDR_RX_DIAG_SC2C_DELAY 0x81e1
73 #define TB_ADDR_RX_REE_VGA_GAIN_NODFE 0x81bf
74 #define TB_ADDR_XCVR_PSM_CAL_TMR 0x4002
75 #define TB_ADDR_XCVR_PSM_A0BYP_TMR 0x4004
76 #define TB_ADDR_XCVR_PSM_A0IN_TMR 0x4003
77 #define TB_ADDR_XCVR_PSM_A1IN_TMR 0x4005
78 #define TB_ADDR_XCVR_PSM_A2IN_TMR 0x4006
79 #define TB_ADDR_XCVR_PSM_A3IN_TMR 0x4007
80 #define TB_ADDR_XCVR_PSM_A4IN_TMR 0x4008
81 #define TB_ADDR_XCVR_PSM_A5IN_TMR 0x4009
82 #define TB_ADDR_XCVR_PSM_A0OUT_TMR 0x400a
83 #define TB_ADDR_XCVR_PSM_A1OUT_TMR 0x400b
84 #define TB_ADDR_XCVR_PSM_A2OUT_TMR 0x400c
85 #define TB_ADDR_XCVR_PSM_A3OUT_TMR 0x400d
86 #define TB_ADDR_XCVR_PSM_A4OUT_TMR 0x400e
87 #define TB_ADDR_XCVR_PSM_A5OUT_TMR 0x400f
88 #define TB_ADDR_TX_RCVDET_EN_TMR 0x4122
89 #define TB_ADDR_TX_RCVDET_ST_TMR 0x4123
90 #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
91 #define TB_ADDR_TX_RCVDETSC_CTRL 0x4124
94 #define UTMI_REG15 0xaf
95 #define UTMI_AFE_RX_REG0 0x0d
96 #define UTMI_AFE_RX_REG5 0x12
97 #define UTMI_AFE_BC_REG4 0x29
101 USB2_DISCONN_THRESHOLD_575 = 0x0,
102 USB2_DISCONN_THRESHOLD_610 = 0x1,
103 USB2_DISCONN_THRESHOLD_645 = 0x3,
109 #define RXDET_IN_P3_32KHZ BIT(0)
117 /* 0us, txvalid is ready just after HS/FS transmitters have powered up */
168 {0x0830, PHY_PMA_CMN_CTRL1},
169 {0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL},
170 {0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR},
171 {0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR},
172 {0x00d0, TB_ADDR_CMN_PLL0_INTDIV},
173 {0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV},
174 {0x0034, TB_ADDR_CMN_PLL0_HIGH_THR},
175 {0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1},
176 {0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2},
177 {0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG},
178 {0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD},
179 {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD},
180 {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD},
181 {0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE},
182 {0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE},
183 {0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG},
184 {0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE},
185 {0x000a, TB_ADDR_CMN_PSM_CLK_CTRL},
186 {0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR},
187 {0xbefc, TB_ADDR_XCVR_PSM_RCTRL},
189 {0x7799, TB_ADDR_TX_PSC_A0},
190 {0x7798, TB_ADDR_TX_PSC_A1},
191 {0x509b, TB_ADDR_TX_PSC_A2},
192 {0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD},
193 {0x509b, TB_ADDR_TX_PSC_A3},
194 {0x2090, TB_ADDR_TX_PSC_CAL},
195 {0x2090, TB_ADDR_TX_PSC_RDY},
197 {0xA6FD, TB_ADDR_RX_PSC_A0},
198 {0xA6FD, TB_ADDR_RX_PSC_A1},
199 {0xA410, TB_ADDR_RX_PSC_A2},
200 {0x2410, TB_ADDR_RX_PSC_A3},
202 {0x23FF, TB_ADDR_RX_PSC_CAL},
203 {0x2010, TB_ADDR_RX_PSC_RDY},
205 {0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000},
206 {0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY},
207 {0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR},
208 {0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR},
209 {0x0000, TB_ADDR_RX_SAMP_DAC_CTRL},
210 {0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE},
211 {0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2},
212 {0x0480, TB_ADDR_RX_DIAG_BS_TM},
213 {0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1},
214 {0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4},
215 {0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0},
216 {0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0},
217 {0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6},
218 {0x8000, TB_ADDR_RX_DIAG_RXFE_TM3},
219 {0x0003, TB_ADDR_RX_DIAG_RXFE_TM4},
220 {0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE},
221 {0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3},
222 {0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY},
223 {0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE},
225 {0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR},
226 {0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR},
227 {0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR},
228 {0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR},
229 {0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR},
230 {0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR},
231 {0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR},
232 {0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR},
234 {0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR},
235 {0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR},
236 {0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR},
237 {0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR},
238 {0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR},
239 {0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR},
241 {0x0960, TB_ADDR_TX_RCVDET_EN_TMR},
242 {0x01e0, TB_ADDR_TX_RCVDET_ST_TMR},
243 {0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR},
257 for (i = 0; i < data->init_sequence_length; i++) { in cdns_salvo_phy_init()
274 cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5, 0x5); in cdns_salvo_phy_init()
301 return 0; in cdns_salvo_phy_power_off()
309 return 0; in cdns_salvo_set_mode()
318 return 0; in cdns_salvo_set_mode()
357 salvo_phy->base = devm_platform_ioremap_resource(pdev, 0); in cdns_salvo_phy_probe()