Lines Matching full:selection

30  * [25] mipi dsi pll clock selection.
33  * [11] mipi divider clk selection.
52 /* [31] clk lane tx_hs_en control selection.
55  * [29] clk lane tx_lp_en contrl selection.
58  * [27] chan0 tx_hs_en control selection.
61  * [25] chan0 tx_lp_en control selection.
64  * [23] chan0 rx_lp_en control selection.
67  * [21] chan0 contention detection enable control selection.
70  * [19] chan1 tx_hs_en control selection.
73  * [17] chan1 tx_lp_en control selection.
76  * [15] chan2 tx_hs_en control selection.
79  * [13] chan2 tx_lp_en control selection.
82  * [11] chan3 tx_hs_en control selection.
85  * [9]  chan3 tx_lp_en control selection.