85 /* A83T specific control bits for PHY2 HSIC */
281 	/* Some PHYs on some SoCs need the help of PHY2 to work. */  in sun4i_usb_phy_init()
283 		struct sun4i_usb_phy *phy2 = &data->phys[2];  in sun4i_usb_phy_init()  local
285 		ret = clk_prepare_enable(phy2->clk);  in sun4i_usb_phy_init()
293 		ret = reset_control_deassert(phy2->reset);  in sun4i_usb_phy_init()
295 			clk_disable_unprepare(phy2->clk);  in sun4i_usb_phy_init()
304 		 * REG_HCI_PHY_CTL PMU register for PHY2.  in sun4i_usb_phy_init()
306 		ret = clk_prepare_enable(phy2->clk2);  in sun4i_usb_phy_init()
308 			reset_control_assert(phy2->reset);  in sun4i_usb_phy_init()
309 			clk_disable_unprepare(phy2->clk);  in sun4i_usb_phy_init()
316 		if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {  in sun4i_usb_phy_init()
317 			val = readl(phy2->pmu + REG_HCI_PHY_CTL);  in sun4i_usb_phy_init()
319 			writel(val, phy2->pmu + REG_HCI_PHY_CTL);  in sun4i_usb_phy_init()
389 		struct sun4i_usb_phy *phy2 = &data->phys[2];  in sun4i_usb_phy_exit()  local
391 		clk_disable_unprepare(phy2->clk);  in sun4i_usb_phy_exit()
392 		reset_control_assert(phy2->reset);  in sun4i_usb_phy_exit()