29 #define HNS3_PMU_REG_GLOBAL_CTRL		0x0000
30 #define HNS3_PMU_REG_CLOCK_FREQ			0x0020
31 #define HNS3_PMU_REG_BDF			0x0fe0
32 #define HNS3_PMU_REG_VERSION			0x0fe4
33 #define HNS3_PMU_REG_DEVICE_ID			0x0fe8
35 #define HNS3_PMU_REG_EVENT_OFFSET		0x1000
36 #define HNS3_PMU_REG_EVENT_SIZE			0x1000
37 #define HNS3_PMU_REG_EVENT_CTRL_LOW		0x00
38 #define HNS3_PMU_REG_EVENT_CTRL_HIGH		0x04
39 #define HNS3_PMU_REG_EVENT_INTR_STATUS		0x08
40 #define HNS3_PMU_REG_EVENT_INTR_MASK		0x0c
41 #define HNS3_PMU_REG_EVENT_COUNTER		0x10
42 #define HNS3_PMU_REG_EVENT_EXT_COUNTER		0x18
43 #define HNS3_PMU_REG_EVENT_QID_CTRL		0x28
44 #define HNS3_PMU_REG_EVENT_QID_PARA		0x2c
46 #define HNS3_PMU_FILTER_SUPPORT_GLOBAL		BIT(0)
53 #define HNS3_PMU_FILTER_ALL_TC			0xf
54 #define HNS3_PMU_FILTER_ALL_QUEUE		0xffff
59 #define HNS3_PMU_GLOBAL_START			BIT(0)
65 #define HNS3_PMU_QID_PARA_FUNC_S		0
68 #define HNS3_PMU_QID_CTRL_REQ_ENABLE		BIT(0)
102  * For example, event 0x00001 and 0x10001 are actually one event for hardware
103  * because bit 0-15 are same. If the bit 16 of one event is 0 means to read
107 #define HNS3_PMU_EVT_BW_SSU_EGU_BYTE_NUM		0x00001
108 #define HNS3_PMU_EVT_BW_SSU_EGU_TIME			0x10001
109 #define HNS3_PMU_EVT_BW_SSU_RPU_BYTE_NUM		0x00002
110 #define HNS3_PMU_EVT_BW_SSU_RPU_TIME			0x10002
111 #define HNS3_PMU_EVT_BW_SSU_ROCE_BYTE_NUM		0x00003
112 #define HNS3_PMU_EVT_BW_SSU_ROCE_TIME			0x10003
113 #define HNS3_PMU_EVT_BW_ROCE_SSU_BYTE_NUM		0x00004
114 #define HNS3_PMU_EVT_BW_ROCE_SSU_TIME			0x10004
115 #define HNS3_PMU_EVT_BW_TPU_SSU_BYTE_NUM		0x00005
116 #define HNS3_PMU_EVT_BW_TPU_SSU_TIME			0x10005
117 #define HNS3_PMU_EVT_BW_RPU_RCBRX_BYTE_NUM		0x00006
118 #define HNS3_PMU_EVT_BW_RPU_RCBRX_TIME			0x10006
119 #define HNS3_PMU_EVT_BW_RCBTX_TXSCH_BYTE_NUM		0x00008
120 #define HNS3_PMU_EVT_BW_RCBTX_TXSCH_TIME		0x10008
121 #define HNS3_PMU_EVT_BW_WR_FBD_BYTE_NUM			0x00009
122 #define HNS3_PMU_EVT_BW_WR_FBD_TIME			0x10009
123 #define HNS3_PMU_EVT_BW_WR_EBD_BYTE_NUM			0x0000a
124 #define HNS3_PMU_EVT_BW_WR_EBD_TIME			0x1000a
125 #define HNS3_PMU_EVT_BW_RD_FBD_BYTE_NUM			0x0000b
126 #define HNS3_PMU_EVT_BW_RD_FBD_TIME			0x1000b
127 #define HNS3_PMU_EVT_BW_RD_EBD_BYTE_NUM			0x0000c
128 #define HNS3_PMU_EVT_BW_RD_EBD_TIME			0x1000c
129 #define HNS3_PMU_EVT_BW_RD_PAY_M0_BYTE_NUM		0x0000d
130 #define HNS3_PMU_EVT_BW_RD_PAY_M0_TIME			0x1000d
131 #define HNS3_PMU_EVT_BW_RD_PAY_M1_BYTE_NUM		0x0000e
132 #define HNS3_PMU_EVT_BW_RD_PAY_M1_TIME			0x1000e
133 #define HNS3_PMU_EVT_BW_WR_PAY_M0_BYTE_NUM		0x0000f
134 #define HNS3_PMU_EVT_BW_WR_PAY_M0_TIME			0x1000f
135 #define HNS3_PMU_EVT_BW_WR_PAY_M1_BYTE_NUM		0x00010
136 #define HNS3_PMU_EVT_BW_WR_PAY_M1_TIME			0x10010
139 #define HNS3_PMU_EVT_PPS_IGU_SSU_PACKET_NUM		0x00100
140 #define HNS3_PMU_EVT_PPS_IGU_SSU_TIME			0x10100
141 #define HNS3_PMU_EVT_PPS_SSU_EGU_PACKET_NUM		0x00101
142 #define HNS3_PMU_EVT_PPS_SSU_EGU_TIME			0x10101
143 #define HNS3_PMU_EVT_PPS_SSU_RPU_PACKET_NUM		0x00102
144 #define HNS3_PMU_EVT_PPS_SSU_RPU_TIME			0x10102
145 #define HNS3_PMU_EVT_PPS_SSU_ROCE_PACKET_NUM		0x00103
146 #define HNS3_PMU_EVT_PPS_SSU_ROCE_TIME			0x10103
147 #define HNS3_PMU_EVT_PPS_ROCE_SSU_PACKET_NUM		0x00104
148 #define HNS3_PMU_EVT_PPS_ROCE_SSU_TIME			0x10104
149 #define HNS3_PMU_EVT_PPS_TPU_SSU_PACKET_NUM		0x00105
150 #define HNS3_PMU_EVT_PPS_TPU_SSU_TIME			0x10105
151 #define HNS3_PMU_EVT_PPS_RPU_RCBRX_PACKET_NUM		0x00106
152 #define HNS3_PMU_EVT_PPS_RPU_RCBRX_TIME			0x10106
153 #define HNS3_PMU_EVT_PPS_RCBTX_TPU_PACKET_NUM		0x00107
154 #define HNS3_PMU_EVT_PPS_RCBTX_TPU_TIME			0x10107
155 #define HNS3_PMU_EVT_PPS_RCBTX_TXSCH_PACKET_NUM		0x00108
156 #define HNS3_PMU_EVT_PPS_RCBTX_TXSCH_TIME		0x10108
157 #define HNS3_PMU_EVT_PPS_WR_FBD_PACKET_NUM		0x00109
158 #define HNS3_PMU_EVT_PPS_WR_FBD_TIME			0x10109
159 #define HNS3_PMU_EVT_PPS_WR_EBD_PACKET_NUM		0x0010a
160 #define HNS3_PMU_EVT_PPS_WR_EBD_TIME			0x1010a
161 #define HNS3_PMU_EVT_PPS_RD_FBD_PACKET_NUM		0x0010b
162 #define HNS3_PMU_EVT_PPS_RD_FBD_TIME			0x1010b
163 #define HNS3_PMU_EVT_PPS_RD_EBD_PACKET_NUM		0x0010c
164 #define HNS3_PMU_EVT_PPS_RD_EBD_TIME			0x1010c
165 #define HNS3_PMU_EVT_PPS_RD_PAY_M0_PACKET_NUM		0x0010d
166 #define HNS3_PMU_EVT_PPS_RD_PAY_M0_TIME			0x1010d
167 #define HNS3_PMU_EVT_PPS_RD_PAY_M1_PACKET_NUM		0x0010e
168 #define HNS3_PMU_EVT_PPS_RD_PAY_M1_TIME			0x1010e
169 #define HNS3_PMU_EVT_PPS_WR_PAY_M0_PACKET_NUM		0x0010f
170 #define HNS3_PMU_EVT_PPS_WR_PAY_M0_TIME			0x1010f
171 #define HNS3_PMU_EVT_PPS_WR_PAY_M1_PACKET_NUM		0x00110
172 #define HNS3_PMU_EVT_PPS_WR_PAY_M1_TIME			0x10110
173 #define HNS3_PMU_EVT_PPS_NICROH_TX_PRE_PACKET_NUM	0x00111
174 #define HNS3_PMU_EVT_PPS_NICROH_TX_PRE_TIME		0x10111
175 #define HNS3_PMU_EVT_PPS_NICROH_RX_PRE_PACKET_NUM	0x00112
176 #define HNS3_PMU_EVT_PPS_NICROH_RX_PRE_TIME		0x10112
179 #define HNS3_PMU_EVT_DLY_TX_PUSH_TIME			0x00202
180 #define HNS3_PMU_EVT_DLY_TX_PUSH_PACKET_NUM		0x10202
181 #define HNS3_PMU_EVT_DLY_TX_TIME			0x00204
182 #define HNS3_PMU_EVT_DLY_TX_PACKET_NUM			0x10204
183 #define HNS3_PMU_EVT_DLY_SSU_TX_NIC_TIME		0x00206
184 #define HNS3_PMU_EVT_DLY_SSU_TX_NIC_PACKET_NUM		0x10206
185 #define HNS3_PMU_EVT_DLY_SSU_TX_ROCE_TIME		0x00207
186 #define HNS3_PMU_EVT_DLY_SSU_TX_ROCE_PACKET_NUM		0x10207
187 #define HNS3_PMU_EVT_DLY_SSU_RX_NIC_TIME		0x00208
188 #define HNS3_PMU_EVT_DLY_SSU_RX_NIC_PACKET_NUM		0x10208
189 #define HNS3_PMU_EVT_DLY_SSU_RX_ROCE_TIME		0x00209
190 #define HNS3_PMU_EVT_DLY_SSU_RX_ROCE_PACKET_NUM		0x10209
191 #define HNS3_PMU_EVT_DLY_RPU_TIME			0x0020e
192 #define HNS3_PMU_EVT_DLY_RPU_PACKET_NUM			0x1020e
193 #define HNS3_PMU_EVT_DLY_TPU_TIME			0x0020f
194 #define HNS3_PMU_EVT_DLY_TPU_PACKET_NUM			0x1020f
195 #define HNS3_PMU_EVT_DLY_RPE_TIME			0x00210
196 #define HNS3_PMU_EVT_DLY_RPE_PACKET_NUM			0x10210
197 #define HNS3_PMU_EVT_DLY_TPE_TIME			0x00211
198 #define HNS3_PMU_EVT_DLY_TPE_PACKET_NUM			0x10211
199 #define HNS3_PMU_EVT_DLY_TPE_PUSH_TIME			0x00212
200 #define HNS3_PMU_EVT_DLY_TPE_PUSH_PACKET_NUM		0x10212
201 #define HNS3_PMU_EVT_DLY_WR_FBD_TIME			0x00213
202 #define HNS3_PMU_EVT_DLY_WR_FBD_PACKET_NUM		0x10213
203 #define HNS3_PMU_EVT_DLY_WR_EBD_TIME			0x00214
204 #define HNS3_PMU_EVT_DLY_WR_EBD_PACKET_NUM		0x10214
205 #define HNS3_PMU_EVT_DLY_RD_FBD_TIME			0x00215
206 #define HNS3_PMU_EVT_DLY_RD_FBD_PACKET_NUM		0x10215
207 #define HNS3_PMU_EVT_DLY_RD_EBD_TIME			0x00216
208 #define HNS3_PMU_EVT_DLY_RD_EBD_PACKET_NUM		0x10216
209 #define HNS3_PMU_EVT_DLY_RD_PAY_M0_TIME			0x00217
210 #define HNS3_PMU_EVT_DLY_RD_PAY_M0_PACKET_NUM		0x10217
211 #define HNS3_PMU_EVT_DLY_RD_PAY_M1_TIME			0x00218
212 #define HNS3_PMU_EVT_DLY_RD_PAY_M1_PACKET_NUM		0x10218
213 #define HNS3_PMU_EVT_DLY_WR_PAY_M0_TIME			0x00219
214 #define HNS3_PMU_EVT_DLY_WR_PAY_M0_PACKET_NUM		0x10219
215 #define HNS3_PMU_EVT_DLY_WR_PAY_M1_TIME			0x0021a
216 #define HNS3_PMU_EVT_DLY_WR_PAY_M1_PACKET_NUM		0x1021a
217 #define HNS3_PMU_EVT_DLY_MSIX_WRITE_TIME		0x0021c
218 #define HNS3_PMU_EVT_DLY_MSIX_WRITE_PACKET_NUM		0x1021c
221 #define HNS3_PMU_EVT_PPS_MSIX_NIC_INTR_NUM		0x00300
222 #define HNS3_PMU_EVT_PPS_MSIX_NIC_TIME			0x10300
225 #define HNS3_PMU_FILTER_BW_SSU_EGU		0x07
226 #define HNS3_PMU_FILTER_BW_SSU_RPU		0x1f
227 #define HNS3_PMU_FILTER_BW_SSU_ROCE		0x0f
228 #define HNS3_PMU_FILTER_BW_ROCE_SSU		0x0f
229 #define HNS3_PMU_FILTER_BW_TPU_SSU		0x1f
230 #define HNS3_PMU_FILTER_BW_RPU_RCBRX		0x11
231 #define HNS3_PMU_FILTER_BW_RCBTX_TXSCH		0x11
232 #define HNS3_PMU_FILTER_BW_WR_FBD		0x1b
233 #define HNS3_PMU_FILTER_BW_WR_EBD		0x11
234 #define HNS3_PMU_FILTER_BW_RD_FBD		0x01
235 #define HNS3_PMU_FILTER_BW_RD_EBD		0x1b
236 #define HNS3_PMU_FILTER_BW_RD_PAY_M0		0x01
237 #define HNS3_PMU_FILTER_BW_RD_PAY_M1		0x01
238 #define HNS3_PMU_FILTER_BW_WR_PAY_M0		0x01
239 #define HNS3_PMU_FILTER_BW_WR_PAY_M1		0x01
242 #define HNS3_PMU_FILTER_PPS_IGU_SSU		0x07
243 #define HNS3_PMU_FILTER_PPS_SSU_EGU		0x07
244 #define HNS3_PMU_FILTER_PPS_SSU_RPU		0x1f
245 #define HNS3_PMU_FILTER_PPS_SSU_ROCE		0x0f
246 #define HNS3_PMU_FILTER_PPS_ROCE_SSU		0x0f
247 #define HNS3_PMU_FILTER_PPS_TPU_SSU		0x1f
248 #define HNS3_PMU_FILTER_PPS_RPU_RCBRX		0x11
249 #define HNS3_PMU_FILTER_PPS_RCBTX_TPU		0x1f
250 #define HNS3_PMU_FILTER_PPS_RCBTX_TXSCH		0x11
251 #define HNS3_PMU_FILTER_PPS_WR_FBD		0x1b
252 #define HNS3_PMU_FILTER_PPS_WR_EBD		0x11
253 #define HNS3_PMU_FILTER_PPS_RD_FBD		0x01
254 #define HNS3_PMU_FILTER_PPS_RD_EBD		0x1b
255 #define HNS3_PMU_FILTER_PPS_RD_PAY_M0		0x01
256 #define HNS3_PMU_FILTER_PPS_RD_PAY_M1		0x01
257 #define HNS3_PMU_FILTER_PPS_WR_PAY_M0		0x01
258 #define HNS3_PMU_FILTER_PPS_WR_PAY_M1		0x01
259 #define HNS3_PMU_FILTER_PPS_NICROH_TX_PRE	0x01
260 #define HNS3_PMU_FILTER_PPS_NICROH_RX_PRE	0x01
263 #define HNS3_PMU_FILTER_DLY_TX_PUSH		0x01
264 #define HNS3_PMU_FILTER_DLY_TX			0x01
265 #define HNS3_PMU_FILTER_DLY_SSU_TX_NIC		0x07
266 #define HNS3_PMU_FILTER_DLY_SSU_TX_ROCE		0x07
267 #define HNS3_PMU_FILTER_DLY_SSU_RX_NIC		0x07
268 #define HNS3_PMU_FILTER_DLY_SSU_RX_ROCE		0x07
269 #define HNS3_PMU_FILTER_DLY_RPU			0x11
270 #define HNS3_PMU_FILTER_DLY_TPU			0x1f
271 #define HNS3_PMU_FILTER_DLY_RPE			0x01
272 #define HNS3_PMU_FILTER_DLY_TPE			0x0b
273 #define HNS3_PMU_FILTER_DLY_TPE_PUSH		0x1b
274 #define HNS3_PMU_FILTER_DLY_WR_FBD		0x1b
275 #define HNS3_PMU_FILTER_DLY_WR_EBD		0x11
276 #define HNS3_PMU_FILTER_DLY_RD_FBD		0x01
277 #define HNS3_PMU_FILTER_DLY_RD_EBD		0x1b
278 #define HNS3_PMU_FILTER_DLY_RD_PAY_M0		0x01
279 #define HNS3_PMU_FILTER_DLY_RD_PAY_M1		0x01
280 #define HNS3_PMU_FILTER_DLY_WR_PAY_M0		0x01
281 #define HNS3_PMU_FILTER_DLY_WR_PAY_M1		0x01
282 #define HNS3_PMU_FILTER_DLY_MSIX_WRITE		0x01
285 #define HNS3_PMU_FILTER_INTR_MSIX_NIC		0x01
318 #define GET_PCI_DEVFN(bdf)  ((bdf) & 0xff)
320 #define FILTER_CONDITION_PORT(port) ((1 << (port)) & 0xff)
321 #define FILTER_CONDITION_PORT_TC(port, tc) (((port) << 3) | ((tc) & 0x07))
331 HNS3_PMU_FILTER_ATTR(subevent, config, 0, 7);
334 HNS3_PMU_FILTER_ATTR(port, config1, 0, 3);
375 	return sysfs_emit(buf, "config=0x%x\n", event->event);  in hns3_pmu_event_show()
389 	len = sysfs_emit_at(buf, 0, "filter mode supported: ");  in hns3_pmu_filter_mode_show()
411 	})[0].attr.attr)
463 	return sysfs_emit(buf, "0x%x\n", hns3_pmu->identifier);  in identifier_show()
652 	HNS3_PMU_FORMAT_ATTR(subevent, "config:0-7"),
655 	HNS3_PMU_FORMAT_ATTR(port, "config1:0-3"),
776 	int hw_event_used = 0;  in hns3_pmu_find_related_event_idx()
779 	for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) {  in hns3_pmu_find_related_event_idx()
806 	for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) {  in hns3_pmu_get_event_idx()
867 	hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_CTRL, idx, 0);  in hns3_pmu_qid_req_start()
888 	for (i = 0; i < ARRAY_SIZE(hns3_pmu_events_attr) - 1; i++) {  in hns3_pmu_get_pmu_event()
912 	return 0;  in hns3_pmu_set_func_mode()
932 	return 0;  in hns3_pmu_set_func_queue_mode()
1027 		return 0;  in hns3_pmu_select_filter_mode()
1038 		return 0;  in hns3_pmu_select_filter_mode()
1043 		return 0;  in hns3_pmu_select_filter_mode()
1048 		return 0;  in hns3_pmu_select_filter_mode()
1061 	event_group[0] = leader;  in hns3_pmu_validate_event_group()
1077 		for (num = 0; num < counters; num++) {  in hns3_pmu_validate_event_group()
1125 	return 0;  in hns3_pmu_get_filter_condition()
1230 	local64_set(&hwc->prev_count, 0);  in hns3_pmu_init_counter()
1231 	hns3_pmu_write_counter(event, 0);  in hns3_pmu_init_counter()
1251 	if (idx < 0) {  in hns3_pmu_event_init()
1275 	return 0;  in hns3_pmu_event_init()
1302 	hwc->state = 0;  in hns3_pmu_start()
1341 	if (idx < 0 && idx != -ENOENT)  in hns3_pmu_add()
1345 	if (idx >= 0 && idx < HNS3_PMU_MAX_HW_EVENTS) {  in hns3_pmu_add()
1351 	if (idx < 0)  in hns3_pmu_add()
1361 	return 0;  in hns3_pmu_add()
1409 	hns3_pmu->bdf_min = val & 0xffff;  in hns3_pmu_alloc_pmu()
1413 	device_id = val & 0xffff;  in hns3_pmu_alloc_pmu()
1438 	return 0;  in hns3_pmu_alloc_pmu()
1446 	for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) {  in hns3_pmu_irq()
1452 		 * As each counter will restart from 0 when it is overflowed,  in hns3_pmu_irq()
1475 	return 0;  in hns3_pmu_online_cpu()
1489 		return 0;  in hns3_pmu_offline_cpu()
1494 		return 0;  in hns3_pmu_offline_cpu()
1500 	return 0;  in hns3_pmu_offline_cpu()
1516 	if (ret < 0) {  in hns3_pmu_irq_register()
1527 	irq = pci_irq_vector(pdev, 0);  in hns3_pmu_irq_register()
1528 	ret = devm_request_irq(&pdev->dev, irq, hns3_pmu_irq, 0,  in hns3_pmu_irq_register()
1537 	return 0;  in hns3_pmu_irq_register()
1589 	if (ret < 0) {  in hns3_pmu_init_dev()
1596 	return 0;  in hns3_pmu_init_dev()
1631 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa22b) },
1632 	{ 0, }