Lines Matching +full:ddr +full:- +full:pmu
1 // SPDX-License-Identifier: GPL-2.0
42 * 32bit counters monitor counter-specific events in addition to counting reference events
59 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
67 const char *identifier; /* system PMU identifier for userspace */
71 struct pmu pmu; member
92 static inline bool is_imx93(struct ddr_pmu *pmu) in is_imx93() argument
94 return pmu->devtype_data == &imx93_devtype_data; in is_imx93()
97 static inline bool is_imx95(struct ddr_pmu *pmu) in is_imx95() argument
99 return pmu->devtype_data == &imx95_devtype_data; in is_imx95()
103 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
104 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
113 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_show() local
115 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
133 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_cpumask_show() local
135 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
162 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
296 struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); in ddr_perf_events_attrs_is_visible() local
297 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); in ddr_perf_events_attrs_is_visible()
302 if (!eattr->devtype_data) in ddr_perf_events_attrs_is_visible()
303 return attr->mode; in ddr_perf_events_attrs_is_visible()
305 if (eattr->devtype_data != ddr_pmu->devtype_data) in ddr_perf_events_attrs_is_visible()
308 return attr->mode; in ddr_perf_events_attrs_is_visible()
317 PMU_FORMAT_ATTR(event, "config:0-7,16-23");
318 PMU_FORMAT_ATTR(counter, "config:8-15");
319 PMU_FORMAT_ATTR(axi_id, "config1:0-17");
320 PMU_FORMAT_ATTR(axi_mask, "config2:0-17");
343 static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_clear_counter() argument
346 writel(0, pmu->base + PMC(counter) + 0x4); in ddr_perf_clear_counter()
347 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
349 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
353 static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_read_counter() argument
359 val = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
365 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4); in ddr_perf_read_counter()
366 val_lower = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
367 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4)); in ddr_perf_read_counter()
376 static void ddr_perf_counter_global_config(struct ddr_pmu *pmu, bool enable) in ddr_perf_counter_global_config() argument
380 ctrl = readl_relaxed(pmu->base + PMGC0); in ddr_perf_counter_global_config()
394 writel(ctrl, pmu->base + PMGC0); in ddr_perf_counter_global_config()
402 writel(ctrl, pmu->base + PMGC0); in ddr_perf_counter_global_config()
406 writel(ctrl, pmu->base + PMGC0); in ddr_perf_counter_global_config()
410 static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, in ddr_perf_counter_local_config() argument
416 ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
421 writel(ctrl_a, pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
423 ddr_perf_clear_counter(pmu, counter); in ddr_perf_counter_local_config()
430 writel(ctrl_a, pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
434 writel(ctrl_a, pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
438 static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, in imx93_ddr_perf_monitor_config() argument
446 pmcfg1 = readl_relaxed(pmu->base + PMCFG1); in imx93_ddr_perf_monitor_config()
449 pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] : in imx93_ddr_perf_monitor_config()
450 pmcfg1 & ~mask[counter - 2]; in imx93_ddr_perf_monitor_config()
454 writel_relaxed(pmcfg1, pmu->base + PMCFG1); in imx93_ddr_perf_monitor_config()
456 pmcfg2 = readl_relaxed(pmu->base + PMCFG2); in imx93_ddr_perf_monitor_config()
459 writel_relaxed(pmcfg2, pmu->base + PMCFG2); in imx93_ddr_perf_monitor_config()
462 static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, in imx95_ddr_perf_monitor_config() argument
467 pmcfg1 = readl_relaxed(pmu->base + PMCFG1); in imx95_ddr_perf_monitor_config()
501 writel_relaxed(pmcfg1, pmu->base + PMCFG1); in imx95_ddr_perf_monitor_config()
504 pmcfg = readl_relaxed(pmu->base + offset); in imx95_ddr_perf_monitor_config()
509 writel_relaxed(pmcfg, pmu->base + offset); in imx95_ddr_perf_monitor_config()
515 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_update() local
516 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_update()
517 int counter = hwc->idx; in ddr_perf_event_update()
520 new_raw_count = ddr_perf_read_counter(pmu, counter); in ddr_perf_event_update()
521 local64_add(new_raw_count, &event->count); in ddr_perf_event_update()
524 ddr_perf_clear_counter(pmu, counter); in ddr_perf_event_update()
529 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_init() local
530 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_init()
533 if (event->attr.type != event->pmu->type) in ddr_perf_event_init()
534 return -ENOENT; in ddr_perf_event_init()
536 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) in ddr_perf_event_init()
537 return -EOPNOTSUPP; in ddr_perf_event_init()
539 if (event->cpu < 0) { in ddr_perf_event_init()
540 dev_warn(pmu->dev, "Can't provide per-task data!\n"); in ddr_perf_event_init()
541 return -EOPNOTSUPP; in ddr_perf_event_init()
547 * periodically read when a hrtimer aka cpu-clock leader triggers). in ddr_perf_event_init()
549 if (event->group_leader->pmu != event->pmu && in ddr_perf_event_init()
550 !is_software_event(event->group_leader)) in ddr_perf_event_init()
551 return -EINVAL; in ddr_perf_event_init()
553 for_each_sibling_event(sibling, event->group_leader) { in ddr_perf_event_init()
554 if (sibling->pmu != event->pmu && in ddr_perf_event_init()
556 return -EINVAL; in ddr_perf_event_init()
559 event->cpu = pmu->cpu; in ddr_perf_event_init()
560 hwc->idx = -1; in ddr_perf_event_init()
567 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_start() local
568 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_start()
569 int counter = hwc->idx; in ddr_perf_event_start()
571 local64_set(&hwc->prev_count, 0); in ddr_perf_event_start()
573 ddr_perf_counter_local_config(pmu, event->attr.config, counter, true); in ddr_perf_event_start()
574 hwc->state = 0; in ddr_perf_event_start()
577 static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter) in ddr_perf_alloc_counter() argument
583 if (pmu->events[CYCLES_COUNTER] == NULL) in ddr_perf_alloc_counter()
587 if (pmu->events[counter] == NULL) in ddr_perf_alloc_counter()
592 if (pmu->events[i] == NULL) in ddr_perf_alloc_counter()
596 return -ENOENT; in ddr_perf_alloc_counter()
601 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_add() local
602 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_add()
603 int cfg = event->attr.config; in ddr_perf_event_add()
604 int cfg1 = event->attr.config1; in ddr_perf_event_add()
605 int cfg2 = event->attr.config2; in ddr_perf_event_add()
611 counter = ddr_perf_alloc_counter(pmu, event_id, counter); in ddr_perf_event_add()
613 dev_dbg(pmu->dev, "There are not enough counters\n"); in ddr_perf_event_add()
614 return -EOPNOTSUPP; in ddr_perf_event_add()
617 pmu->events[counter] = event; in ddr_perf_event_add()
618 pmu->active_events++; in ddr_perf_event_add()
619 hwc->idx = counter; in ddr_perf_event_add()
620 hwc->state |= PERF_HES_STOPPED; in ddr_perf_event_add()
622 if (is_imx93(pmu)) in ddr_perf_event_add()
624 imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); in ddr_perf_event_add()
626 if (is_imx95(pmu)) in ddr_perf_event_add()
628 imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); in ddr_perf_event_add()
638 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_stop() local
639 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_stop()
640 int counter = hwc->idx; in ddr_perf_event_stop()
642 ddr_perf_counter_local_config(pmu, event->attr.config, counter, false); in ddr_perf_event_stop()
645 hwc->state |= PERF_HES_STOPPED; in ddr_perf_event_stop()
650 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_del() local
651 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_del()
652 int counter = hwc->idx; in ddr_perf_event_del()
656 pmu->events[counter] = NULL; in ddr_perf_event_del()
657 pmu->active_events--; in ddr_perf_event_del()
658 hwc->idx = -1; in ddr_perf_event_del()
661 static void ddr_perf_pmu_enable(struct pmu *pmu) in ddr_perf_pmu_enable() argument
663 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); in ddr_perf_pmu_enable()
668 static void ddr_perf_pmu_disable(struct pmu *pmu) in ddr_perf_pmu_disable() argument
670 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); in ddr_perf_pmu_disable()
675 static void ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, in ddr_perf_init() argument
678 *pmu = (struct ddr_pmu) { in ddr_perf_init()
679 .pmu = (struct pmu) { in ddr_perf_init()
700 struct ddr_pmu *pmu = (struct ddr_pmu *)p; in ddr_perf_irq_handler() local
716 if (!pmu->events[i]) in ddr_perf_irq_handler()
719 event = pmu->events[i]; in ddr_perf_irq_handler()
724 ddr_perf_counter_global_config(pmu, true); in ddr_perf_irq_handler()
731 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node); in ddr_perf_offline_cpu() local
734 if (cpu != pmu->cpu) in ddr_perf_offline_cpu()
741 perf_pmu_migrate_context(&pmu->pmu, cpu, target); in ddr_perf_offline_cpu()
742 pmu->cpu = target; in ddr_perf_offline_cpu()
744 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu))); in ddr_perf_offline_cpu()
751 struct ddr_pmu *pmu; in ddr_perf_probe() local
760 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); in ddr_perf_probe()
761 if (!pmu) in ddr_perf_probe()
762 return -ENOMEM; in ddr_perf_probe()
764 ddr_perf_init(pmu, base, &pdev->dev); in ddr_perf_probe()
766 pmu->devtype_data = of_device_get_match_data(&pdev->dev); in ddr_perf_probe()
768 platform_set_drvdata(pdev, pmu); in ddr_perf_probe()
770 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL); in ddr_perf_probe()
771 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", pmu->id); in ddr_perf_probe()
773 ret = -ENOMEM; in ddr_perf_probe()
777 pmu->cpu = raw_smp_processor_id(); in ddr_perf_probe()
781 dev_err(&pdev->dev, "Failed to add callbacks for multi state\n"); in ddr_perf_probe()
784 pmu->cpuhp_state = ret; in ddr_perf_probe()
786 /* Register the pmu instance for cpu hotplug */ in ddr_perf_probe()
787 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
789 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); in ddr_perf_probe()
800 ret = devm_request_irq(&pdev->dev, irq, ddr_perf_irq_handler, in ddr_perf_probe()
802 DDR_CPUHP_CB_NAME, pmu); in ddr_perf_probe()
804 dev_err(&pdev->dev, "Request irq failed: %d", ret); in ddr_perf_probe()
808 pmu->irq = irq; in ddr_perf_probe()
809 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)); in ddr_perf_probe()
811 dev_err(pmu->dev, "Failed to set interrupt affinity\n"); in ddr_perf_probe()
815 ret = perf_pmu_register(&pmu->pmu, name, -1); in ddr_perf_probe()
822 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
824 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_probe()
827 ida_free(&ddr_ida, pmu->id); in ddr_perf_probe()
828 dev_warn(&pdev->dev, "i.MX9 DDR Perf PMU failed (%d), disabled\n", ret); in ddr_perf_probe()
834 struct ddr_pmu *pmu = platform_get_drvdata(pdev); in ddr_perf_remove() local
836 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_remove()
837 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_remove()
839 perf_pmu_unregister(&pmu->pmu); in ddr_perf_remove()
841 ida_free(&ddr_ida, pmu->id); in ddr_perf_remove()
846 .name = "imx9-ddr-pmu",