Lines Matching +full:0 +full:x12210
37 #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
38 #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
39 #define ARMV7_PERFCTR_ITLB_REFILL 0x02
40 #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
41 #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
42 #define ARMV7_PERFCTR_DTLB_REFILL 0x05
43 #define ARMV7_PERFCTR_MEM_READ 0x06
44 #define ARMV7_PERFCTR_MEM_WRITE 0x07
45 #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
46 #define ARMV7_PERFCTR_EXC_TAKEN 0x09
47 #define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
48 #define ARMV7_PERFCTR_CID_WRITE 0x0B
57 #define ARMV7_PERFCTR_PC_WRITE 0x0C
58 #define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
59 #define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
60 #define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
61 #define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
62 #define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
63 #define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
66 #define ARMV7_PERFCTR_MEM_ACCESS 0x13
67 #define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
68 #define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
69 #define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
70 #define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
71 #define ARMV7_PERFCTR_L2_CACHE_WB 0x18
72 #define ARMV7_PERFCTR_BUS_ACCESS 0x19
73 #define ARMV7_PERFCTR_MEM_ERROR 0x1A
74 #define ARMV7_PERFCTR_INSTR_SPEC 0x1B
75 #define ARMV7_PERFCTR_TTBR_WRITE 0x1C
76 #define ARMV7_PERFCTR_BUS_CYCLES 0x1D
78 #define ARMV7_PERFCTR_CPU_CYCLES 0xFF
81 #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
82 #define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
83 #define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
84 #define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
87 #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
88 #define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
89 #define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
92 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
93 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
96 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
97 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
98 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
99 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
101 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
102 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
104 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
105 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
106 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
107 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
109 #define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
112 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
113 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
115 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
116 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
118 #define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
120 #define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
123 #define KRAIT_PMRESR0_GROUP0 0xcc
124 #define KRAIT_PMRESR1_GROUP0 0xd0
125 #define KRAIT_PMRESR2_GROUP0 0xd4
126 #define KRAIT_VPMRESR0_GROUP0 0xd8
128 #define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
129 #define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
131 #define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
132 #define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
135 #define SCORPION_LPM0_GROUP0 0x4c
136 #define SCORPION_LPM1_GROUP0 0x50
137 #define SCORPION_LPM2_GROUP0 0x54
138 #define SCORPION_L2LPM_GROUP0 0x58
139 #define SCORPION_VLPM_GROUP0 0x5c
141 #define SCORPION_ICACHE_ACCESS 0x10053
142 #define SCORPION_ICACHE_MISS 0x10052
144 #define SCORPION_DTLB_ACCESS 0x12013
145 #define SCORPION_DTLB_MISS 0x12012
147 #define SCORPION_ITLB_MISS 0x12021
533 PMU_FORMAT_ATTR(event, "config:0-7");
661 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
668 #define ARMV7_PMNC_N_MASK 0x1f
669 #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
674 #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
680 #define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */
681 #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
698 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); in armv7_pmnc_read()
706 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); in armv7_pmnc_write()
726 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (idx)); in armv7_pmnc_select_counter()
735 u32 value = 0; in armv7pmu_read_counter()
741 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); in armv7pmu_read_counter()
744 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); in armv7pmu_read_counter()
760 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value)); in armv7pmu_write_counter()
763 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value)); in armv7pmu_write_counter()
771 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); in armv7_pmnc_write_evtsel()
776 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(idx))); in armv7_pmnc_enable_counter()
781 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(idx))); in armv7_pmnc_disable_counter()
786 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(idx))); in armv7_pmnc_enable_intens()
791 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(idx))); in armv7_pmnc_disable_intens()
794 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(idx))); in armv7_pmnc_disable_intens()
803 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); in armv7_pmnc_getreset_flags()
807 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); in armv7_pmnc_getreset_flags()
820 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); in armv7_pmnc_dump_regs()
821 pr_info("PMNC =0x%08x\n", val); in armv7_pmnc_dump_regs()
823 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
824 pr_info("CNTENS=0x%08x\n", val); in armv7_pmnc_dump_regs()
826 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
827 pr_info("INTENS=0x%08x\n", val); in armv7_pmnc_dump_regs()
829 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); in armv7_pmnc_dump_regs()
830 pr_info("FLAGS =0x%08x\n", val); in armv7_pmnc_dump_regs()
832 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); in armv7_pmnc_dump_regs()
833 pr_info("SELECT=0x%08x\n", val); in armv7_pmnc_dump_regs()
835 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); in armv7_pmnc_dump_regs()
836 pr_info("CCNT =0x%08x\n", val); in armv7_pmnc_dump_regs()
840 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); in armv7_pmnc_dump_regs()
841 pr_info("CNT[%d] count =0x%08x\n", cnt, val); in armv7_pmnc_dump_regs()
842 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
843 pr_info("CNT[%d] evtsel=0x%08x\n", cnt, val); in armv7_pmnc_dump_regs()
957 perf_sample_data_init(&data, 0, hwc->last_period); in armv7pmu_handle_irq()
1030 unsigned long config_base = 0; in armv7pmu_set_event_filter()
1049 return 0; in armv7pmu_set_event_filter()
1058 asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); in armv7pmu_reset()
1060 asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); in armv7pmu_reset()
1076 &armv7_a8_perf_cache_map, 0xFF); in armv7_a8_map_event()
1082 &armv7_a9_perf_cache_map, 0xFF); in armv7_a9_map_event()
1088 &armv7_a5_perf_cache_map, 0xFF); in armv7_a5_map_event()
1094 &armv7_a15_perf_cache_map, 0xFF); in armv7_a15_map_event()
1100 &armv7_a7_perf_cache_map, 0xFF); in armv7_a7_map_event()
1106 &armv7_a12_perf_cache_map, 0xFF); in armv7_a12_map_event()
1112 &krait_perf_cache_map, 0xFFFFF); in krait_map_event()
1118 &krait_perf_cache_map, 0xFFFFF); in krait_map_event_no_branch()
1124 &scorpion_perf_cache_map, 0xFFFFF); in scorpion_map_event()
1148 bitmap_set(cpu_pmu->cntr_mask, 0, nb_cnt); in armv7_read_num_pmnc_events()
1250 * 31 30 24 16 8 0
1252 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0
1260 * EN | G=3 | G=2 | G=1 | G=0
1264 * hwc->config_base = 0xNRCCG
1271 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
1285 #define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */
1286 #define EVENT_GROUP(event) ((event) & 0xf) /* G */
1287 #define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */
1296 case 0: in krait_read_pmresrn()
1297 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); in krait_read_pmresrn()
1300 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); in krait_read_pmresrn()
1303 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); in krait_read_pmresrn()
1315 case 0: in krait_write_pmresrn()
1316 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); in krait_write_pmresrn()
1319 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); in krait_write_pmresrn()
1322 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); in krait_write_pmresrn()
1332 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); in venum_read_pmresr()
1338 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); in venum_write_pmresr()
1388 mask = 0xff << group_shift; in krait_evt_setup()
1423 mask = 0xff << group_shift; in clear_pmresrn_group()
1430 return 0; in clear_pmresrn_group()
1513 krait_write_pmresrn(0, 0); in krait_pmu_reset()
1514 krait_write_pmresrn(1, 0); in krait_pmu_reset()
1515 krait_write_pmresrn(2, 0); in krait_pmu_reset()
1518 venum_write_pmresr(0); in krait_pmu_reset()
1524 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); in krait_pmu_reset()
1540 bit -= krait_get_pmresrn_event(0); in krait_event_to_bit()
1571 if (venum_event && (code & 0xe0)) in krait_pmu_get_event_idx()
1580 if (idx < 0 && bit >= 0) in krait_pmu_get_event_idx()
1625 * 31 30 24 16 8 0
1627 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0
1637 * EN | G=3 | G=2 | G=1 | G=0
1642 * hwc->config_base = 0xNRCCG
1649 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2
1663 case 0: in scorpion_read_pmresrn()
1664 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); in scorpion_read_pmresrn()
1667 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); in scorpion_read_pmresrn()
1670 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); in scorpion_read_pmresrn()
1673 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); in scorpion_read_pmresrn()
1685 case 0: in scorpion_write_pmresrn()
1686 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); in scorpion_write_pmresrn()
1689 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); in scorpion_write_pmresrn()
1692 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); in scorpion_write_pmresrn()
1695 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); in scorpion_write_pmresrn()
1723 mask = 0xff << group_shift; in scorpion_evt_setup()
1735 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); in scorpion_evt_setup()
1834 scorpion_write_pmresrn(0, 0); in scorpion_pmu_reset()
1835 scorpion_write_pmresrn(1, 0); in scorpion_pmu_reset()
1836 scorpion_write_pmresrn(2, 0); in scorpion_pmu_reset()
1837 scorpion_write_pmresrn(3, 0); in scorpion_pmu_reset()
1840 venum_write_pmresr(0); in scorpion_pmu_reset()
1846 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); in scorpion_pmu_reset()
1861 bit -= scorpion_get_pmresrn_event(0); in scorpion_event_to_bit()
1898 if (idx < 0 && bit >= 0) in scorpion_pmu_get_event_idx()