Lines Matching +full:dt +full:- +full:node
1 // SPDX-License-Identifier: GPL-2.0-only
112 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
120 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
121 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
143 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
164 struct hlist_node node; member
178 struct arm_ccn_component *node; member
183 struct arm_ccn_dt dt; member
187 static int arm_ccn_node_to_xp(int node) in arm_ccn_node_to_xp() argument
189 return node / CCN_NUM_XP_PORTS; in arm_ccn_node_to_xp()
192 static int arm_ccn_node_to_xp_port(int node) in arm_ccn_node_to_xp_port() argument
194 return node % CCN_NUM_XP_PORTS; in arm_ccn_node_to_xp_port()
223 static CCN_FORMAT_ATTR(node, "config:0-7");
224 static CCN_FORMAT_ATTR(xp, "config:0-7");
225 static CCN_FORMAT_ATTR(type, "config:8-15");
226 static CCN_FORMAT_ATTR(event, "config:16-23");
227 static CCN_FORMAT_ATTR(port, "config:24-25");
228 static CCN_FORMAT_ATTR(bus, "config:24-25");
229 static CCN_FORMAT_ATTR(vc, "config:26-28");
230 static CCN_FORMAT_ATTR(dir, "config:29-29");
231 static CCN_FORMAT_ATTR(mask, "config:30-33");
232 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
233 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
270 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
300 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
322 res = sysfs_emit(buf, "type=0x%x", event->type); in arm_ccn_pmu_event_show()
323 if (event->event) in arm_ccn_pmu_event_show()
324 res += sysfs_emit_at(buf, res, ",event=0x%x", event->event); in arm_ccn_pmu_event_show()
325 if (event->def) in arm_ccn_pmu_event_show()
326 res += sysfs_emit_at(buf, res, ",%s", event->def); in arm_ccn_pmu_event_show()
327 if (event->mask) in arm_ccn_pmu_event_show()
328 res += sysfs_emit_at(buf, res, ",mask=0x%x", event->mask); in arm_ccn_pmu_event_show()
331 switch (event->type) { in arm_ccn_pmu_event_show()
336 if (event->event == CCN_EVENT_WATCHPOINT) in arm_ccn_pmu_event_show()
344 res += sysfs_emit_at(buf, res, ",node=%d", ccn->mn_id); in arm_ccn_pmu_event_show()
347 res += sysfs_emit_at(buf, res, ",node=?"); in arm_ccn_pmu_event_show()
366 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present) in arm_ccn_pmu_events_is_visible()
368 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present) in arm_ccn_pmu_events_is_visible()
371 return attr->mode; in arm_ccn_pmu_events_is_visible()
447 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a'; in arm_ccn_pmu_get_cmp_mask()
451 return &ccn->dt.cmp_mask[i].l; in arm_ccn_pmu_get_cmp_mask()
453 return &ccn->dt.cmp_mask[i].h; in arm_ccn_pmu_get_cmp_mask()
463 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); in arm_ccn_pmu_cmp_mask_show()
465 return mask ? sysfs_emit(buf, "0x%016llx\n", *mask) : -EINVAL; in arm_ccn_pmu_cmp_mask_show()
472 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); in arm_ccn_pmu_cmp_mask_store()
473 int err = -EINVAL; in arm_ccn_pmu_cmp_mask_store()
541 return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu)); in arm_ccn_pmu_cpumask_show()
588 return -EAGAIN; in arm_ccn_pmu_alloc_bit()
594 /* All RN-I and RN-D nodes have identical PMUs */
624 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_alloc()
625 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_alloc()
630 node_xp = CCN_CONFIG_NODE(event->attr.config); in arm_ccn_pmu_event_alloc()
631 type = CCN_CONFIG_TYPE(event->attr.config); in arm_ccn_pmu_event_alloc()
632 event_id = CCN_CONFIG_EVENT(event->attr.config); in arm_ccn_pmu_event_alloc()
637 ccn->dt.pmu_counters_mask)) in arm_ccn_pmu_event_alloc()
638 return -EAGAIN; in arm_ccn_pmu_event_alloc()
640 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER; in arm_ccn_pmu_event_alloc()
641 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; in arm_ccn_pmu_event_alloc()
647 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_event_alloc()
649 if (hw->idx < 0) { in arm_ccn_pmu_event_alloc()
650 dev_dbg(ccn->dev, "No more counters available!\n"); in arm_ccn_pmu_event_alloc()
651 return -EAGAIN; in arm_ccn_pmu_event_alloc()
655 source = &ccn->xp[node_xp]; in arm_ccn_pmu_event_alloc()
657 source = &ccn->node[node_xp]; in arm_ccn_pmu_event_alloc()
658 ccn->dt.pmu_counters[hw->idx].source = source; in arm_ccn_pmu_event_alloc()
662 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask, in arm_ccn_pmu_event_alloc()
665 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask, in arm_ccn_pmu_event_alloc()
668 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n", in arm_ccn_pmu_event_alloc()
670 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_alloc()
671 return -EAGAIN; in arm_ccn_pmu_event_alloc()
673 hw->config_base = bit; in arm_ccn_pmu_event_alloc()
675 ccn->dt.pmu_counters[hw->idx].event = event; in arm_ccn_pmu_event_alloc()
682 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_release()
683 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_release()
685 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) { in arm_ccn_pmu_event_release()
686 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
689 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_event_release()
691 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP && in arm_ccn_pmu_event_release()
692 CCN_CONFIG_EVENT(event->attr.config) == in arm_ccn_pmu_event_release()
694 clear_bit(hw->config_base, source->xp.dt_cmp_mask); in arm_ccn_pmu_event_release()
696 clear_bit(hw->config_base, source->pmu_events_mask); in arm_ccn_pmu_event_release()
697 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
700 ccn->dt.pmu_counters[hw->idx].source = NULL; in arm_ccn_pmu_event_release()
701 ccn->dt.pmu_counters[hw->idx].event = NULL; in arm_ccn_pmu_event_release()
707 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_init()
713 if (event->attr.type != event->pmu->type) in arm_ccn_pmu_event_init()
714 return -ENOENT; in arm_ccn_pmu_event_init()
716 ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_init()
718 if (hw->sample_period) { in arm_ccn_pmu_event_init()
719 dev_dbg(ccn->dev, "Sampling not supported!\n"); in arm_ccn_pmu_event_init()
720 return -EOPNOTSUPP; in arm_ccn_pmu_event_init()
724 dev_dbg(ccn->dev, "Can't exclude execution levels!\n"); in arm_ccn_pmu_event_init()
725 return -EINVAL; in arm_ccn_pmu_event_init()
728 if (event->cpu < 0) { in arm_ccn_pmu_event_init()
729 dev_dbg(ccn->dev, "Can't provide per-task data!\n"); in arm_ccn_pmu_event_init()
730 return -EOPNOTSUPP; in arm_ccn_pmu_event_init()
736 * but can lead to issues for off-core PMUs, like CCN, where each in arm_ccn_pmu_event_init()
741 event->cpu = ccn->dt.cpu; in arm_ccn_pmu_event_init()
743 node_xp = CCN_CONFIG_NODE(event->attr.config); in arm_ccn_pmu_event_init()
744 type = CCN_CONFIG_TYPE(event->attr.config); in arm_ccn_pmu_event_init()
745 event_id = CCN_CONFIG_EVENT(event->attr.config); in arm_ccn_pmu_event_init()
747 /* Validate node/xp vs topology */ in arm_ccn_pmu_event_init()
750 if (node_xp != ccn->mn_id) { in arm_ccn_pmu_event_init()
751 dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp); in arm_ccn_pmu_event_init()
752 return -EINVAL; in arm_ccn_pmu_event_init()
756 if (node_xp >= ccn->num_xps) { in arm_ccn_pmu_event_init()
757 dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp); in arm_ccn_pmu_event_init()
758 return -EINVAL; in arm_ccn_pmu_event_init()
764 if (node_xp >= ccn->num_nodes) { in arm_ccn_pmu_event_init()
765 dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp); in arm_ccn_pmu_event_init()
766 return -EINVAL; in arm_ccn_pmu_event_init()
768 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) { in arm_ccn_pmu_event_init()
769 dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n", in arm_ccn_pmu_event_init()
771 return -EINVAL; in arm_ccn_pmu_event_init()
780 u32 port = CCN_CONFIG_PORT(event->attr.config); in arm_ccn_pmu_event_init()
781 u32 vc = CCN_CONFIG_VC(event->attr.config); in arm_ccn_pmu_event_init()
783 if (!arm_ccn_pmu_type_eq(type, e->type)) in arm_ccn_pmu_event_init()
785 if (event_id != e->event) in arm_ccn_pmu_event_init()
787 if (e->num_ports && port >= e->num_ports) { in arm_ccn_pmu_event_init()
788 dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n", in arm_ccn_pmu_event_init()
790 return -EINVAL; in arm_ccn_pmu_event_init()
792 if (e->num_vcs && vc >= e->num_vcs) { in arm_ccn_pmu_event_init()
793 dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n", in arm_ccn_pmu_event_init()
795 return -EINVAL; in arm_ccn_pmu_event_init()
800 dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n", in arm_ccn_pmu_event_init()
802 return -EINVAL; in arm_ccn_pmu_event_init()
805 /* Watchpoint-based event for a node is actually set on XP */ in arm_ccn_pmu_event_init()
813 arm_ccn_pmu_config_set(&event->attr.config, in arm_ccn_pmu_event_init()
820 * periodically read when a hrtimer aka cpu-clock leader triggers). in arm_ccn_pmu_event_init()
822 if (event->group_leader->pmu != event->pmu && in arm_ccn_pmu_event_init()
823 !is_software_event(event->group_leader)) in arm_ccn_pmu_event_init()
824 return -EINVAL; in arm_ccn_pmu_event_init()
826 for_each_sibling_event(sibling, event->group_leader) { in arm_ccn_pmu_event_init()
827 if (sibling->pmu != event->pmu && in arm_ccn_pmu_event_init()
829 return -EINVAL; in arm_ccn_pmu_event_init()
841 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); in arm_ccn_pmu_read_counter()
844 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); in arm_ccn_pmu_read_counter()
845 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) in arm_ccn_pmu_read_counter()
847 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_read_counter()
848 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; in arm_ccn_pmu_read_counter()
850 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); in arm_ccn_pmu_read_counter()
853 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); in arm_ccn_pmu_read_counter()
861 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_update()
862 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_update()
866 prev_count = local64_read(&hw->prev_count); in arm_ccn_pmu_event_update()
867 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx); in arm_ccn_pmu_event_update()
868 } while (local64_xchg(&hw->prev_count, new_count) != prev_count); in arm_ccn_pmu_event_update()
870 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1; in arm_ccn_pmu_event_update()
872 local64_add((new_count - prev_count) & mask, &event->count); in arm_ccn_pmu_event_update()
877 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_xp_dt_config()
878 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_xp_dt_config()
883 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) in arm_ccn_pmu_xp_dt_config()
886 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) in arm_ccn_pmu_xp_dt_config()
887 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)]; in arm_ccn_pmu_xp_dt_config()
889 xp = &ccn->xp[arm_ccn_node_to_xp( in arm_ccn_pmu_xp_dt_config()
890 CCN_CONFIG_NODE(event->attr.config))]; in arm_ccn_pmu_xp_dt_config()
893 dt_cfg = hw->event_base; in arm_ccn_pmu_xp_dt_config()
897 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
899 val = readl(xp->base + CCN_XP_DT_CONFIG); in arm_ccn_pmu_xp_dt_config()
901 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx)); in arm_ccn_pmu_xp_dt_config()
902 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx); in arm_ccn_pmu_xp_dt_config()
903 writel(val, xp->base + CCN_XP_DT_CONFIG); in arm_ccn_pmu_xp_dt_config()
905 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
910 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_start()
911 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_start()
913 local64_set(&event->hw.prev_count, in arm_ccn_pmu_event_start()
914 arm_ccn_pmu_read_counter(ccn, hw->idx)); in arm_ccn_pmu_event_start()
915 hw->state = 0; in arm_ccn_pmu_event_start()
917 /* Set the DT bus input, engaging the counter */ in arm_ccn_pmu_event_start()
923 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_stop()
925 /* Disable counting, setting the DT bus to pass-through mode */ in arm_ccn_pmu_event_stop()
931 hw->state |= PERF_HES_STOPPED; in arm_ccn_pmu_event_stop()
936 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_xp_watchpoint_config()
937 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_xp_watchpoint_config()
939 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_watchpoint_config()
940 unsigned long wp = hw->config_base; in arm_ccn_pmu_xp_watchpoint_config()
942 u64 cmp_l = event->attr.config1; in arm_ccn_pmu_xp_watchpoint_config()
943 u64 cmp_h = event->attr.config2; in arm_ccn_pmu_xp_watchpoint_config()
944 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; in arm_ccn_pmu_xp_watchpoint_config()
945 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; in arm_ccn_pmu_xp_watchpoint_config()
947 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); in arm_ccn_pmu_xp_watchpoint_config()
950 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); in arm_ccn_pmu_xp_watchpoint_config()
953 val |= CCN_CONFIG_DIR(event->attr.config) << in arm_ccn_pmu_xp_watchpoint_config()
957 val |= CCN_CONFIG_PORT(event->attr.config) << in arm_ccn_pmu_xp_watchpoint_config()
961 val |= CCN_CONFIG_VC(event->attr.config) << in arm_ccn_pmu_xp_watchpoint_config()
963 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); in arm_ccn_pmu_xp_watchpoint_config()
966 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); in arm_ccn_pmu_xp_watchpoint_config()
968 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
969 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); in arm_ccn_pmu_xp_watchpoint_config()
971 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
974 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); in arm_ccn_pmu_xp_watchpoint_config()
976 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
977 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); in arm_ccn_pmu_xp_watchpoint_config()
979 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
984 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_xp_event_config()
985 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_xp_event_config()
987 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_event_config()
990 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
992 id = (CCN_CONFIG_VC(event->attr.config) << 4) | in arm_ccn_pmu_xp_event_config()
993 (CCN_CONFIG_BUS(event->attr.config) << 3) | in arm_ccn_pmu_xp_event_config()
994 (CCN_CONFIG_EVENT(event->attr.config) << 0); in arm_ccn_pmu_xp_event_config()
996 val = readl(source->base + CCN_XP_PMU_EVENT_SEL); in arm_ccn_pmu_xp_event_config()
998 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_xp_event_config()
999 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1000 writel(val, source->base + CCN_XP_PMU_EVENT_SEL); in arm_ccn_pmu_xp_event_config()
1005 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_node_event_config()
1006 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_node_event_config()
1008 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_node_event_config()
1009 u32 type = CCN_CONFIG_TYPE(event->attr.config); in arm_ccn_pmu_node_event_config()
1012 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config)); in arm_ccn_pmu_node_event_config()
1013 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, in arm_ccn_pmu_node_event_config()
1014 hw->config_base); in arm_ccn_pmu_node_event_config()
1031 /* Set the event id for the pre-allocated counter */ in arm_ccn_pmu_node_event_config()
1032 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); in arm_ccn_pmu_node_event_config()
1034 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_node_event_config()
1035 val |= CCN_CONFIG_EVENT(event->attr.config) << in arm_ccn_pmu_node_event_config()
1036 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_node_event_config()
1037 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); in arm_ccn_pmu_node_event_config()
1042 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_config()
1043 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_config()
1047 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) in arm_ccn_pmu_event_config()
1050 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) in arm_ccn_pmu_event_config()
1051 xp = CCN_CONFIG_XP(event->attr.config); in arm_ccn_pmu_event_config()
1053 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config)); in arm_ccn_pmu_event_config()
1055 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1057 /* Set the DT bus "distance" register */ in arm_ccn_pmu_event_config()
1058 offset = (hw->idx / 4) * 4; in arm_ccn_pmu_event_config()
1059 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1061 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4)); in arm_ccn_pmu_event_config()
1062 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4); in arm_ccn_pmu_event_config()
1063 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1065 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) { in arm_ccn_pmu_event_config()
1066 if (CCN_CONFIG_EVENT(event->attr.config) == in arm_ccn_pmu_event_config()
1075 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1080 return bitmap_weight(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_active_counters()
1087 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_add()
1088 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_add()
1096 * event->cpu (this is the same one as presented in "cpumask" in arm_ccn_pmu_event_add()
1099 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1) in arm_ccn_pmu_event_add()
1100 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), in arm_ccn_pmu_event_add()
1105 hw->state = PERF_HES_STOPPED; in arm_ccn_pmu_event_add()
1115 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_del()
1121 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0) in arm_ccn_pmu_event_del()
1122 hrtimer_cancel(&ccn->dt.hrtimer); in arm_ccn_pmu_event_del()
1134 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1136 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1143 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1145 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1148 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) in arm_ccn_pmu_overflow_handler() argument
1150 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); in arm_ccn_pmu_overflow_handler()
1156 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_overflow_handler()
1161 struct perf_event *event = dt->pmu_counters[idx].event; in arm_ccn_pmu_overflow_handler()
1178 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, in arm_ccn_pmu_timer_handler() local
1183 arm_ccn_pmu_overflow_handler(dt); in arm_ccn_pmu_timer_handler()
1191 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) in arm_ccn_pmu_offline_cpu() argument
1193 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); in arm_ccn_pmu_offline_cpu() local
1194 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); in arm_ccn_pmu_offline_cpu()
1197 if (cpu != dt->cpu) in arm_ccn_pmu_offline_cpu()
1202 perf_pmu_migrate_context(&dt->pmu, cpu, target); in arm_ccn_pmu_offline_cpu()
1203 dt->cpu = target; in arm_ccn_pmu_offline_cpu()
1204 if (ccn->irq) in arm_ccn_pmu_offline_cpu()
1205 WARN_ON(irq_set_affinity(ccn->irq, cpumask_of(dt->cpu))); in arm_ccn_pmu_offline_cpu()
1217 /* Initialize DT subsystem */ in arm_ccn_pmu_init()
1218 ccn->dt.base = ccn->base + CCN_REGION_SIZE; in arm_ccn_pmu_init()
1219 spin_lock_init(&ccn->dt.config_lock); in arm_ccn_pmu_init()
1220 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_init()
1221 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); in arm_ccn_pmu_init()
1223 ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1224 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_init()
1225 for (i = 0; i < ccn->num_xps; i++) { in arm_ccn_pmu_init()
1226 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG); in arm_ccn_pmu_init()
1232 ccn->xp[i].base + CCN_XP_DT_CONTROL); in arm_ccn_pmu_init()
1234 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; in arm_ccn_pmu_init()
1235 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; in arm_ccn_pmu_init()
1236 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; in arm_ccn_pmu_init()
1237 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; in arm_ccn_pmu_init()
1238 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; in arm_ccn_pmu_init()
1239 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); in arm_ccn_pmu_init()
1240 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; in arm_ccn_pmu_init()
1241 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); in arm_ccn_pmu_init()
1244 ccn->dt.id = ida_alloc(&arm_ccn_pmu_ida, GFP_KERNEL); in arm_ccn_pmu_init()
1245 if (ccn->dt.id == 0) { in arm_ccn_pmu_init()
1248 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d", in arm_ccn_pmu_init()
1249 ccn->dt.id); in arm_ccn_pmu_init()
1251 err = -ENOMEM; in arm_ccn_pmu_init()
1257 ccn->dt.pmu = (struct pmu) { in arm_ccn_pmu_init()
1259 .parent = ccn->dev, in arm_ccn_pmu_init()
1274 if (!ccn->irq) { in arm_ccn_pmu_init()
1275 dev_info(ccn->dev, "No access to interrupts, using timer.\n"); in arm_ccn_pmu_init()
1276 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, in arm_ccn_pmu_init()
1278 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; in arm_ccn_pmu_init()
1282 ccn->dt.cpu = raw_smp_processor_id(); in arm_ccn_pmu_init()
1285 if (ccn->irq) { in arm_ccn_pmu_init()
1286 err = irq_set_affinity(ccn->irq, cpumask_of(ccn->dt.cpu)); in arm_ccn_pmu_init()
1288 dev_err(ccn->dev, "Failed to set interrupt affinity!\n"); in arm_ccn_pmu_init()
1294 &ccn->dt.node); in arm_ccn_pmu_init()
1296 err = perf_pmu_register(&ccn->dt.pmu, name, -1); in arm_ccn_pmu_init()
1304 &ccn->dt.node); in arm_ccn_pmu_init()
1307 ida_free(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_init()
1308 for (i = 0; i < ccn->num_xps; i++) in arm_ccn_pmu_init()
1309 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); in arm_ccn_pmu_init()
1310 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1319 &ccn->dt.node); in arm_ccn_pmu_cleanup()
1320 for (i = 0; i < ccn->num_xps; i++) in arm_ccn_pmu_cleanup()
1321 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); in arm_ccn_pmu_cleanup()
1322 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_cleanup()
1323 perf_pmu_unregister(&ccn->dt.pmu); in arm_ccn_pmu_cleanup()
1324 ida_free(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_cleanup()
1338 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + in arm_ccn_for_each_valid_region()
1343 base = ccn->base + region * CCN_REGION_SIZE; in arm_ccn_for_each_valid_region()
1362 if (type == CCN_TYPE_XP && id >= ccn->num_xps) in arm_ccn_get_nodes_num()
1363 ccn->num_xps = id + 1; in arm_ccn_get_nodes_num()
1364 else if (id >= ccn->num_nodes) in arm_ccn_get_nodes_num()
1365 ccn->num_nodes = id + 1; in arm_ccn_get_nodes_num()
1375 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type); in arm_ccn_init_nodes()
1379 ccn->mn_id = id; in arm_ccn_init_nodes()
1384 component = &ccn->xp[id]; in arm_ccn_init_nodes()
1387 ccn->sbsx_present = 1; in arm_ccn_init_nodes()
1388 component = &ccn->node[id]; in arm_ccn_init_nodes()
1391 ccn->sbas_present = 1; in arm_ccn_init_nodes()
1394 component = &ccn->node[id]; in arm_ccn_init_nodes()
1398 component->base = base; in arm_ccn_init_nodes()
1399 component->type = type; in arm_ccn_init_nodes()
1409 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n", in arm_ccn_error_handler()
1412 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n"); in arm_ccn_error_handler()
1414 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_error_handler()
1429 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0); in arm_ccn_irq_handler()
1432 res = arm_ccn_pmu_overflow_handler(&ccn->dt); in arm_ccn_irq_handler()
1437 err_sig_val[i] = readl(ccn->base + in arm_ccn_irq_handler()
1446 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_irq_handler()
1458 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL); in arm_ccn_probe()
1460 return -ENOMEM; in arm_ccn_probe()
1461 ccn->dev = &pdev->dev; in arm_ccn_probe()
1464 ccn->base = devm_platform_ioremap_resource(pdev, 0); in arm_ccn_probe()
1465 if (IS_ERR(ccn->base)) in arm_ccn_probe()
1466 return PTR_ERR(ccn->base); in arm_ccn_probe()
1474 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_probe()
1475 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) & in arm_ccn_probe()
1479 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_probe()
1480 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, in arm_ccn_probe()
1482 dev_name(ccn->dev), ccn); in arm_ccn_probe()
1486 ccn->irq = irq; in arm_ccn_probe()
1496 ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node), in arm_ccn_probe()
1498 ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node), in arm_ccn_probe()
1500 if (!ccn->node || !ccn->xp) in arm_ccn_probe()
1501 return -ENOMEM; in arm_ccn_probe()
1518 { .compatible = "arm,ccn-502", },
1519 { .compatible = "arm,ccn-504", },
1520 { .compatible = "arm,ccn-512", },
1527 .name = "arm-ccn",