120 #define CCN_NUM_XP_WATCHPOINTS		2 /* See DT.dbg_id.num_watchpoints */
121 #define CCN_NUM_PMU_EVENT_COUNTERS	8 /* See DT.dbg_id.num_pmucntr */
143 	struct arm_ccn_dt, pmu), struct arm_ccn, dt)
183 	struct arm_ccn_dt dt;  member
451 		return &ccn->dt.cmp_mask[i].l;  in arm_ccn_pmu_get_cmp_mask()
453 		return &ccn->dt.cmp_mask[i].h;  in arm_ccn_pmu_get_cmp_mask()
541 	return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu));  in arm_ccn_pmu_cpumask_show()
637 				ccn->dt.pmu_counters_mask))  in arm_ccn_pmu_event_alloc()
641 		ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;  in arm_ccn_pmu_event_alloc()
647 	hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,  in arm_ccn_pmu_event_alloc()
658 	ccn->dt.pmu_counters[hw->idx].source = source;  in arm_ccn_pmu_event_alloc()
670 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_alloc()
675 	ccn->dt.pmu_counters[hw->idx].event = event;  in arm_ccn_pmu_event_alloc()
686 		clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_release()
689 				ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_event_release()
697 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_release()
700 	ccn->dt.pmu_counters[hw->idx].source = NULL;  in arm_ccn_pmu_event_release()
701 	ccn->dt.pmu_counters[hw->idx].event = NULL;  in arm_ccn_pmu_event_release()
741 	event->cpu = ccn->dt.cpu;  in arm_ccn_pmu_event_init()
841 		res = readq(ccn->dt.base + CCN_DT_PMCCNTR);  in arm_ccn_pmu_read_counter()
844 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);  in arm_ccn_pmu_read_counter()
845 		while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))  in arm_ccn_pmu_read_counter()
847 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_read_counter()
848 		res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;  in arm_ccn_pmu_read_counter()
850 		res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);  in arm_ccn_pmu_read_counter()
853 		res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));  in arm_ccn_pmu_read_counter()
897 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
905 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
917 	/* Set the DT bus input, engaging the counter */  in arm_ccn_pmu_event_start()
925 	/* Disable counting, setting the DT bus to pass-through mode */  in arm_ccn_pmu_event_stop()
939 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_watchpoint_config()
944 	u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;  in arm_ccn_pmu_xp_watchpoint_config()
945 	u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;  in arm_ccn_pmu_xp_watchpoint_config()
987 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_event_config()
1008 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_node_event_config()
1055 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
1057 	/* Set the DT bus "distance" register */  in arm_ccn_pmu_event_config()
1059 	val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1063 	writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1075 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
1080 	return bitmap_weight(ccn->dt.pmu_counters_mask,  in arm_ccn_pmu_active_counters()
1100 		hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),  in arm_ccn_pmu_event_add()
1122 		hrtimer_cancel(&ccn->dt.hrtimer);  in arm_ccn_pmu_event_del()
1134 	u32 val = readl(ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_enable()
1136 	writel(val, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_enable()
1143 	u32 val = readl(ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_disable()
1145 	writel(val, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_disable()
1148 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)  in arm_ccn_pmu_overflow_handler()  argument
1150 	u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);  in arm_ccn_pmu_overflow_handler()
1156 	writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_overflow_handler()
1161 		struct perf_event *event = dt->pmu_counters[idx].event;  in arm_ccn_pmu_overflow_handler()
1178 	struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,  in arm_ccn_pmu_timer_handler()  local
1183 	arm_ccn_pmu_overflow_handler(dt);  in arm_ccn_pmu_timer_handler()
1193 	struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);  in arm_ccn_pmu_offline_cpu()  local
1194 	struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);  in arm_ccn_pmu_offline_cpu()
1197 	if (cpu != dt->cpu)  in arm_ccn_pmu_offline_cpu()
1202 	perf_pmu_migrate_context(&dt->pmu, cpu, target);  in arm_ccn_pmu_offline_cpu()
1203 	dt->cpu = target;  in arm_ccn_pmu_offline_cpu()
1205 		WARN_ON(irq_set_affinity(ccn->irq, cpumask_of(dt->cpu)));  in arm_ccn_pmu_offline_cpu()
1217 	/* Initialize DT subsystem */  in arm_ccn_pmu_init()
1218 	ccn->dt.base = ccn->base + CCN_REGION_SIZE;  in arm_ccn_pmu_init()
1219 	spin_lock_init(&ccn->dt.config_lock);  in arm_ccn_pmu_init()
1220 	writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_init()
1221 	writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);  in arm_ccn_pmu_init()
1223 			ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_init()
1224 	writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_init()
1234 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;  in arm_ccn_pmu_init()
1235 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;  in arm_ccn_pmu_init()
1236 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;  in arm_ccn_pmu_init()
1237 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;  in arm_ccn_pmu_init()
1238 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;  in arm_ccn_pmu_init()
1239 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);  in arm_ccn_pmu_init()
1240 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;  in arm_ccn_pmu_init()
1241 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);  in arm_ccn_pmu_init()
1244 	ccn->dt.id = ida_alloc(&arm_ccn_pmu_ida, GFP_KERNEL);  in arm_ccn_pmu_init()
1245 	if (ccn->dt.id == 0) {  in arm_ccn_pmu_init()
1249 				      ccn->dt.id);  in arm_ccn_pmu_init()
1257 	ccn->dt.pmu = (struct pmu) {  in arm_ccn_pmu_init()
1276 		hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,  in arm_ccn_pmu_init()
1278 		ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;  in arm_ccn_pmu_init()
1282 	ccn->dt.cpu = raw_smp_processor_id();  in arm_ccn_pmu_init()
1286 		err = irq_set_affinity(ccn->irq, cpumask_of(ccn->dt.cpu));  in arm_ccn_pmu_init()
1294 					 &ccn->dt.node);  in arm_ccn_pmu_init()
1296 	err = perf_pmu_register(&ccn->dt.pmu, name, -1);  in arm_ccn_pmu_init()
1304 					    &ccn->dt.node);  in arm_ccn_pmu_init()
1307 	ida_free(&arm_ccn_pmu_ida, ccn->dt.id);  in arm_ccn_pmu_init()
1310 	writel(0, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_init()
1319 					    &ccn->dt.node);  in arm_ccn_pmu_cleanup()
1322 	writel(0, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_cleanup()
1323 	perf_pmu_unregister(&ccn->dt.pmu);  in arm_ccn_pmu_cleanup()
1324 	ida_free(&arm_ccn_pmu_ida, ccn->dt.id);  in arm_ccn_pmu_cleanup()
1432 		res = arm_ccn_pmu_overflow_handler(&ccn->dt);  in arm_ccn_irq_handler()