drivers/perf/arm-cci.c

140 #define CCI_EVENT_EXT_ATTR_ENTRY(_name, _config) \  macro
219 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0),
220 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01),
221 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2),
222 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3),
223 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4),
224 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5),
225 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6),
226 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
227 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8),
228 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9),
229 	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA),
230 	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB),
231 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC),
232 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD),
233 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE),
234 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF),
235 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10),
236 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11),
237 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12),
238 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13),
240 	CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x14),
241 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_addr_hazard, 0x15),
242 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_id_hazard, 0x16),
243 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_tt_full, 0x17),
244 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x18),
245 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x19),
246 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_tt_full, 0x1A),
254 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0),
255 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01),
256 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2),
257 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3),
258 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4),
259 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5),
260 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6),
261 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
262 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8),
263 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9),
264 	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA),
265 	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB),
266 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC),
267 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD),
268 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE),
269 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF),
270 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10),
271 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11),
272 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12),
273 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13),
274 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_slave_id_hazard, 0x14),
276 	CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x0),
277 	CCI_EVENT_EXT_ATTR_ENTRY(mi_stall_cycle_addr_hazard, 0x1),
278 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_master_id_hazard, 0x2),
279 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_hi_prio_rtq_full, 0x3),
280 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x4),
281 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x5),
282 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_wtq_full, 0x6),
283 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_low_prio_rtq_full, 0x7),
284 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_mid_prio_rtq_full, 0x8),
285 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn0, 0x9),
286 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn1, 0xA),
287 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn2, 0xB),
288 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn3, 0xC),
289 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn0, 0xD),
290 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn1, 0xE),
291 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn2, 0xF),
292 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn3, 0x10),
293 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_unique_or_line_unique_addr_hazard, 0x11),
455 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_arvalid, 0x0),
456 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_dev, 0x1),
457 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_nonshareable, 0x2),
458 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_non_alloc, 0x3),
459 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_alloc, 0x4),
460 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_invalidate, 0x5),
461 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maint, 0x6),
462 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
463 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rval, 0x8),
464 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rlast_snoop, 0x9),
465 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_awalid, 0xA),
466 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_dev, 0xB),
467 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_non_shareable, 0xC),
468 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wb, 0xD),
469 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wlu, 0xE),
470 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wunique, 0xF),
471 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_evict, 0x10),
472 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_wrevict, 0x11),
473 	CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_beat, 0x12),
474 	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_acvalid, 0x13),
475 	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_read, 0x14),
476 	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_clean, 0x15),
477 	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_data_transfer_low, 0x16),
478 	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_arvalid, 0x17),
479 	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall, 0x18),
480 	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall, 0x19),
481 	CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_stall, 0x1A),
482 	CCI_EVENT_EXT_ATTR_ENTRY(si_w_resp_stall, 0x1B),
483 	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_stall, 0x1C),
484 	CCI_EVENT_EXT_ATTR_ENTRY(si_s_data_stall, 0x1D),
485 	CCI_EVENT_EXT_ATTR_ENTRY(si_rq_stall_ot_limit, 0x1E),
486 	CCI_EVENT_EXT_ATTR_ENTRY(si_r_stall_arbit, 0x1F),
489 	CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_beat_any, 0x0),
490 	CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_beat_any, 0x1),
491 	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall, 0x2),
492 	CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_stall, 0x3),
493 	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall, 0x4),
494 	CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_stall, 0x5),
495 	CCI_EVENT_EXT_ATTR_ENTRY(mi_w_resp_stall, 0x6),