1 // SPDX-License-Identifier: GPL-2.0
43 PMU_FORMAT_ATTR(event, "config:0-7");
127 /* calculate ddr clock */
135 	val = readl(info->pll_reg);  in dmc_g12_get_freq_quick()
179 		r  = readl(db->ddr_reg[0] + (DMC_MON_G12_CTRL0 + (i << 2)));  in g12_dump_reg()
182 	r  = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT);  in g12_dump_reg()
184 	r  = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT);  in g12_dump_reg()
186 	r  = readl(db->ddr_reg[0] + DMC_MON_G12_ONE_GRANT_CNT);  in g12_dump_reg()
188 	r  = readl(db->ddr_reg[0] + DMC_MON_G12_SEC_GRANT_CNT);  in g12_dump_reg()
190 	r  = readl(db->ddr_reg[0] + DMC_MON_G12_THD_GRANT_CNT);  in g12_dump_reg()
192 	r  = readl(db->ddr_reg[0] + DMC_MON_G12_FOR_GRANT_CNT);  in g12_dump_reg()
194 	r  = readl(db->ddr_reg[0] + DMC_MON_G12_TIMER);  in g12_dump_reg()
204 	writel(clock_count, info->ddr_reg[0] + DMC_MON_G12_TIMER);  in dmc_g12_counter_enable()
206 	val = readl(info->ddr_reg[0] + DMC_MON_G12_CTRL0);  in dmc_g12_counter_enable()
213 	writel(val, info->ddr_reg[0] + DMC_MON_G12_CTRL0);  in dmc_g12_counter_enable()
228 	int subport = -1;  in dmc_g12_config_fiter()
232 		writel(0, info->ddr_reg[0] + rp[channel]);  in dmc_g12_config_fiter()
233 		writel(0, info->ddr_reg[0] + rs[channel]);  in dmc_g12_config_fiter()
238 		subport = port - PORT_MAJOR;  in dmc_g12_config_fiter()
241 		val = readl(info->ddr_reg[0] + rp[channel]);  in dmc_g12_config_fiter()
243 		writel(val, info->ddr_reg[0] + rp[channel]);  in dmc_g12_config_fiter()
245 		writel(val, info->ddr_reg[0] + rs[channel]);  in dmc_g12_config_fiter()
248 		writel(val, info->ddr_reg[0] + rp[channel]);  in dmc_g12_config_fiter()
249 		val = readl(info->ddr_reg[0] + rs[channel]);  in dmc_g12_config_fiter()
251 		writel(val, info->ddr_reg[0] + rs[channel]);  in dmc_g12_config_fiter()
257 	if (channel > info->hw_info->chann_nr)  in dmc_g12_set_axi_filter()
268 	writel(0, info->ddr_reg[0] + DMC_MON_G12_CTRL0);  in dmc_g12_counter_disable()
269 	writel(0, info->ddr_reg[0] + DMC_MON_G12_TIMER);  in dmc_g12_counter_disable()
271 	writel(0, info->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT);  in dmc_g12_counter_disable()
272 	writel(0, info->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT);  in dmc_g12_counter_disable()
273 	writel(0, info->ddr_reg[0] + DMC_MON_G12_ONE_GRANT_CNT);  in dmc_g12_counter_disable()
274 	writel(0, info->ddr_reg[0] + DMC_MON_G12_SEC_GRANT_CNT);  in dmc_g12_counter_disable()
275 	writel(0, info->ddr_reg[0] + DMC_MON_G12_THD_GRANT_CNT);  in dmc_g12_counter_disable()
276 	writel(0, info->ddr_reg[0] + DMC_MON_G12_FOR_GRANT_CNT);  in dmc_g12_counter_disable()
279 	for (i = 0; i < info->hw_info->chann_nr; i++)  in dmc_g12_counter_disable()
280 		dmc_g12_config_fiter(info, -1, i);  in dmc_g12_counter_disable()
289 	counter->all_cnt = readl(info->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT);  in dmc_g12_get_counters()
290 	counter->all_req   = readl(info->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT);  in dmc_g12_get_counters()
292 	for (i = 0; i < info->hw_info->chann_nr; i++) {  in dmc_g12_get_counters()
294 		counter->channel_cnt[i] = readl(info->ddr_reg[0] + reg);  in dmc_g12_get_counters()
302 	int ret = -EINVAL;  in dmc_g12_irq_handler()
304 	val = readl(info->ddr_reg[0] + DMC_MON_G12_CTRL0);  in dmc_g12_irq_handler()
308 		writel(val, info->ddr_reg[0] + DMC_MON_G12_CTRL0);  in dmc_g12_irq_handler()
365 		.compatible = "amlogic,g12a-ddr-pmu",
369 		.compatible = "amlogic,g12b-ddr-pmu",
373 		.compatible = "amlogic,sm1-ddr-pmu",
385 		.name = "meson-g12-ddr-pmu",
393 MODULE_DESCRIPTION("Amlogic G12 series SoC DDR PMU");