Lines Matching +full:x +full:- +full:max
1 // SPDX-License-Identifier: GPL-2.0
51 if (r->domain_nr == domain_nr) in get_pci_domain_busn_res()
52 return &r->res; in get_pci_domain_busn_res()
58 r->domain_nr = domain_nr; in get_pci_domain_busn_res()
59 r->res.start = 0; in get_pci_domain_busn_res()
60 r->res.end = 0xff; in get_pci_domain_busn_res()
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; in get_pci_domain_busn_res()
63 list_add_tail(&r->list, &pci_domain_busn_res_list); in get_pci_domain_busn_res()
65 return &r->res; in get_pci_domain_busn_res()
92 put_device(pci_bus->bridge); in release_pcibus_dev()
120 size = size & ~(size-1); in pci_size()
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) in pci_size()
153 /* 1M mem BAR treated as 32-bit BAR */ in decode_bar()
159 /* mem unknown type treated as 32-bit BAR */ in decode_bar()
168 * __pci_read_base - Read a PCI BAR
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
183 const char *res_name = pci_resource_name(dev, res - dev->resource); in __pci_read_base()
188 if (!dev->mmio_always_on) { in __pci_read_base()
196 res->name = pci_name(dev); in __pci_read_base()
220 res->flags = decode_bar(dev, l); in __pci_read_base()
221 res->flags |= IORESOURCE_SIZEALIGN; in __pci_read_base()
222 if (res->flags & IORESOURCE_IO) { in __pci_read_base()
233 res->flags |= IORESOURCE_ROM_ENABLE; in __pci_read_base()
239 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) in __pci_read_base()
262 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; in __pci_read_base()
266 res->start = 0; in __pci_read_base()
267 res->end = 0; in __pci_read_base()
274 /* Above 32-bit boundary; try to reallocate */ in __pci_read_base()
275 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
276 res->start = 0; in __pci_read_base()
277 res->end = sz64 - 1; in __pci_read_base()
285 region.end = l64 + sz64 - 1; in __pci_read_base()
287 pcibios_bus_to_resource(dev->bus, res, ®ion); in __pci_read_base()
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); in __pci_read_base()
302 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
303 res->start = 0; in __pci_read_base()
304 res->end = region.end - region.start; in __pci_read_base()
313 res->flags = 0; in __pci_read_base()
315 if (res->flags) in __pci_read_base()
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; in __pci_read_base()
325 if (dev->non_compliant_bars) in pci_read_bases()
329 if (dev->is_virtfn) in pci_read_bases()
333 struct resource *res = &dev->resource[pos]; in pci_read_bases()
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; in pci_read_bases()
340 dev->rom_base_reg = rom; in pci_read_bases()
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | in pci_read_bases()
356 if (dev->io_window_1k) { in pci_read_bridge_io()
377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; in pci_read_bridge_io()
379 region.end = limit + io_granularity - 1; in pci_read_bridge_io()
380 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_io()
398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; in pci_read_bridge_mmio()
401 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio()
447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | in pci_read_bridge_mmio_pref()
449 if (res->flags & PCI_PREF_RANGE_TYPE_64) in pci_read_bridge_mmio_pref()
450 res->flags |= IORESOURCE_MEM_64; in pci_read_bridge_mmio_pref()
453 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio_pref()
471 bridge->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_windows()
480 bridge->io_window = 1; in pci_read_bridge_windows()
491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) in pci_read_bridge_windows()
504 bridge->pref_window = 1; in pci_read_bridge_windows()
509 * Bridge claims to have a 64-bit prefetchable memory in pci_read_bridge_windows()
519 bridge->pref_64_window = 1; in pci_read_bridge_windows()
527 struct pci_dev *dev = child->self; in pci_read_bridge_bases()
535 &child->busn_res, in pci_read_bridge_bases()
536 dev->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_bases()
540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; in pci_read_bridge_bases()
542 pci_read_bridge_io(child->self, child->resource[0], false); in pci_read_bridge_bases()
543 pci_read_bridge_mmio(child->self, child->resource[1], false); in pci_read_bridge_bases()
544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false); in pci_read_bridge_bases()
546 if (dev->transparent) { in pci_read_bridge_bases()
547 pci_bus_for_each_resource(child->parent, res) { in pci_read_bridge_bases()
548 if (res && res->flags) { in pci_read_bridge_bases()
566 INIT_LIST_HEAD(&b->node); in pci_alloc_bus()
567 INIT_LIST_HEAD(&b->children); in pci_alloc_bus()
568 INIT_LIST_HEAD(&b->devices); in pci_alloc_bus()
569 INIT_LIST_HEAD(&b->slots); in pci_alloc_bus()
570 INIT_LIST_HEAD(&b->resources); in pci_alloc_bus()
571 b->max_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
572 b->cur_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
575 b->domain_nr = parent->domain_nr; in pci_alloc_bus()
584 if (bridge->release_fn) in pci_release_host_bridge_dev()
585 bridge->release_fn(bridge); in pci_release_host_bridge_dev()
587 pci_free_resource_list(&bridge->windows); in pci_release_host_bridge_dev()
588 pci_free_resource_list(&bridge->dma_ranges); in pci_release_host_bridge_dev()
594 INIT_LIST_HEAD(&bridge->windows); in pci_init_host_bridge()
595 INIT_LIST_HEAD(&bridge->dma_ranges); in pci_init_host_bridge()
603 bridge->native_aer = 1; in pci_init_host_bridge()
604 bridge->native_pcie_hotplug = 1; in pci_init_host_bridge()
605 bridge->native_shpc_hotplug = 1; in pci_init_host_bridge()
606 bridge->native_pme = 1; in pci_init_host_bridge()
607 bridge->native_ltr = 1; in pci_init_host_bridge()
608 bridge->native_dpc = 1; in pci_init_host_bridge()
609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; in pci_init_host_bridge()
610 bridge->native_cxl_error = 1; in pci_init_host_bridge()
612 device_initialize(&bridge->dev); in pci_init_host_bridge()
624 bridge->dev.release = pci_release_host_bridge_dev; in pci_alloc_host_bridge()
645 bridge->dev.parent = dev; in devm_pci_alloc_host_bridge()
662 put_device(&bridge->dev); in pci_free_host_bridge()
713 "66 MHz PCI-X", /* 0x02 */ in pci_speed_string()
714 "100 MHz PCI-X", /* 0x03 */ in pci_speed_string()
715 "133 MHz PCI-X", /* 0x04 */ in pci_speed_string()
720 "66 MHz PCI-X 266", /* 0x09 */ in pci_speed_string()
721 "100 MHz PCI-X 266", /* 0x0a */ in pci_speed_string()
722 "133 MHz PCI-X 266", /* 0x0b */ in pci_speed_string()
724 "1x AGP", /* 0x0d */ in pci_speed_string()
725 "2x AGP", /* 0x0e */ in pci_speed_string()
726 "4x AGP", /* 0x0f */ in pci_speed_string()
727 "8x AGP", /* 0x10 */ in pci_speed_string()
728 "66 MHz PCI-X 533", /* 0x11 */ in pci_speed_string()
729 "100 MHz PCI-X 533", /* 0x12 */ in pci_speed_string()
730 "133 MHz PCI-X 533", /* 0x13 */ in pci_speed_string()
747 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; in pcie_update_link_speed()
784 struct pci_dev *bridge = bus->self; in pci_set_bus_speed()
794 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); in pci_set_bus_speed()
797 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); in pci_set_bus_speed()
803 enum pci_bus_speed max; in pci_set_bus_speed() local
809 max = PCI_SPEED_133MHz_PCIX_533; in pci_set_bus_speed()
811 max = PCI_SPEED_133MHz_PCIX_266; in pci_set_bus_speed()
814 max = PCI_SPEED_133MHz_PCIX_ECC; in pci_set_bus_speed()
816 max = PCI_SPEED_133MHz_PCIX; in pci_set_bus_speed()
818 max = PCI_SPEED_66MHz_PCIX; in pci_set_bus_speed()
821 bus->max_bus_speed = max; in pci_set_bus_speed()
822 bus->cur_bus_speed = in pci_set_bus_speed()
833 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; in pci_set_bus_speed()
845 d = dev_get_msi_domain(bus->bridge); in pci_host_bridge_msi_domain()
878 * created by an SR-IOV device. Walk up to the first bridge device in pci_set_bus_msi_domain()
881 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { in pci_set_bus_msi_domain()
882 if (b->self) in pci_set_bus_msi_domain()
883 d = dev_get_msi_domain(&b->self->dev); in pci_set_bus_msi_domain()
889 dev_set_msi_domain(&bus->dev, d); in pci_set_bus_msi_domain()
897 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node) in pci_preserve_config()
898 return of_pci_preserve_config(host_bridge->dev.parent->of_node); in pci_preserve_config()
905 struct device *parent = bridge->dev.parent; in pci_register_host_bridge()
917 return -ENOMEM; in pci_register_host_bridge()
919 bridge->bus = bus; in pci_register_host_bridge()
921 bus->sysdata = bridge->sysdata; in pci_register_host_bridge()
922 bus->ops = bridge->ops; in pci_register_host_bridge()
923 bus->number = bus->busn_res.start = bridge->busnr; in pci_register_host_bridge()
925 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) in pci_register_host_bridge()
926 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); in pci_register_host_bridge()
928 bus->domain_nr = bridge->domain_nr; in pci_register_host_bridge()
929 if (bus->domain_nr < 0) { in pci_register_host_bridge()
930 err = bus->domain_nr; in pci_register_host_bridge()
935 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); in pci_register_host_bridge()
938 dev_dbg(&b->dev, "bus already known\n"); in pci_register_host_bridge()
939 err = -EEXIST; in pci_register_host_bridge()
943 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), in pci_register_host_bridge()
944 bridge->busnr); in pci_register_host_bridge()
951 list_splice_init(&bridge->windows, &resources); in pci_register_host_bridge()
952 err = device_add(&bridge->dev); in pci_register_host_bridge()
954 put_device(&bridge->dev); in pci_register_host_bridge()
957 bus->bridge = get_device(&bridge->dev); in pci_register_host_bridge()
958 device_enable_async_suspend(bus->bridge); in pci_register_host_bridge()
961 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && in pci_register_host_bridge()
963 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in pci_register_host_bridge()
966 set_dev_node(bus->bridge, pcibus_to_node(bus)); in pci_register_host_bridge()
968 bus->dev.class = &pcibus_class; in pci_register_host_bridge()
969 bus->dev.parent = bus->bridge; in pci_register_host_bridge()
971 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); in pci_register_host_bridge()
972 name = dev_name(&bus->dev); in pci_register_host_bridge()
974 err = device_register(&bus->dev); in pci_register_host_bridge()
980 if (bus->ops->add_bus) { in pci_register_host_bridge()
981 err = bus->ops->add_bus(bus); in pci_register_host_bridge()
983 dev_err(&bus->dev, "failed to add bus: %d\n", err); in pci_register_host_bridge()
995 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); in pci_register_host_bridge()
998 bridge->preserve_config = pci_preserve_config(bridge); in pci_register_host_bridge()
1002 if (list_is_last(&window->node, &resources)) in pci_register_host_bridge()
1006 offset = window->offset; in pci_register_host_bridge()
1007 res = window->res; in pci_register_host_bridge()
1008 next_offset = next->offset; in pci_register_host_bridge()
1009 next_res = next->res; in pci_register_host_bridge()
1011 if (res->flags != next_res->flags || offset != next_offset) in pci_register_host_bridge()
1014 if (res->end + 1 == next_res->start) { in pci_register_host_bridge()
1015 next_res->start = res->start; in pci_register_host_bridge()
1016 res->flags = res->start = res->end = 0; in pci_register_host_bridge()
1022 offset = window->offset; in pci_register_host_bridge()
1023 res = window->res; in pci_register_host_bridge()
1024 if (!res->flags && !res->start && !res->end) { in pci_register_host_bridge()
1030 list_move_tail(&window->node, &bridge->windows); in pci_register_host_bridge()
1032 if (res->flags & IORESOURCE_BUS) in pci_register_host_bridge()
1033 pci_bus_insert_busn_res(bus, bus->number, res->end); in pci_register_host_bridge()
1039 fmt = " (bus address [%#06llx-%#06llx])"; in pci_register_host_bridge()
1041 fmt = " (bus address [%#010llx-%#010llx])"; in pci_register_host_bridge()
1044 (unsigned long long)(res->start - offset), in pci_register_host_bridge()
1045 (unsigned long long)(res->end - offset)); in pci_register_host_bridge()
1049 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); in pci_register_host_bridge()
1053 list_add_tail(&bus->node, &pci_root_buses); in pci_register_host_bridge()
1059 put_device(&bridge->dev); in pci_register_host_bridge()
1060 device_del(&bridge->dev); in pci_register_host_bridge()
1064 pci_bus_release_domain_nr(parent, bus->domain_nr); in pci_register_host_bridge()
1079 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_bridge_child_ext_cfg_accessible()
1095 * - PCI-to-PCI bridges in pci_bridge_child_ext_cfg_accessible()
1096 * - PCIe-to-PCI/PCI-X forward bridges in pci_bridge_child_ext_cfg_accessible()
1097 * - PCI/PCI-X-to-PCIe reverse bridges in pci_bridge_child_ext_cfg_accessible()
1099 * if the bridge supports PCI-X Mode 2. in pci_bridge_child_ext_cfg_accessible()
1122 child->parent = parent; in pci_alloc_child_bus()
1123 child->sysdata = parent->sysdata; in pci_alloc_child_bus()
1124 child->bus_flags = parent->bus_flags; in pci_alloc_child_bus()
1127 if (host->child_ops) in pci_alloc_child_bus()
1128 child->ops = host->child_ops; in pci_alloc_child_bus()
1130 child->ops = parent->ops; in pci_alloc_child_bus()
1136 child->dev.class = &pcibus_class; in pci_alloc_child_bus()
1137 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); in pci_alloc_child_bus()
1140 child->number = child->busn_res.start = busnr; in pci_alloc_child_bus()
1141 child->primary = parent->busn_res.start; in pci_alloc_child_bus()
1142 child->busn_res.end = 0xff; in pci_alloc_child_bus()
1145 child->dev.parent = parent->bridge; in pci_alloc_child_bus()
1149 child->self = bridge; in pci_alloc_child_bus()
1150 child->bridge = get_device(&bridge->dev); in pci_alloc_child_bus()
1151 child->dev.parent = child->bridge; in pci_alloc_child_bus()
1161 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; in pci_alloc_child_bus()
1167 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; in pci_alloc_child_bus()
1168 child->resource[i]->name = child->name; in pci_alloc_child_bus()
1170 bridge->subordinate = child; in pci_alloc_child_bus()
1174 ret = device_register(&child->dev); in pci_alloc_child_bus()
1179 if (child->ops->add_bus) { in pci_alloc_child_bus()
1180 ret = child->ops->add_bus(child); in pci_alloc_child_bus()
1182 dev_err(&child->dev, "failed to add bus: %d\n", ret); in pci_alloc_child_bus()
1199 list_add_tail(&child->node, &parent->children); in pci_add_new_bus()
1215 pdev->config_rrs_sv = 1; in pci_enable_rrs_sv()
1222 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1238 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) in pci_ea_fixed_busnrs()
1259 * pci_scan_bridge_extend() - Scan buses behind a bridge
1262 * @max: Starting subordinate number of buses behind this bridge
1266 * distributed equally between hotplug-capable bridges.
1274 * We need to process bridges in two passes -- first we scan those
1282 int max, unsigned int available_buses, in pci_scan_bridge_extend() argument
1286 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); in pci_scan_bridge_extend()
1299 pm_runtime_get_sync(&dev->dev); in pci_scan_bridge_extend()
1306 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", in pci_scan_bridge_extend()
1309 if (!primary && (primary != bus->number) && secondary && subordinate) { in pci_scan_bridge_extend()
1311 primary = bus->number; in pci_scan_bridge_extend()
1316 (primary != bus->number || secondary <= bus->number || in pci_scan_bridge_extend()
1318 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", in pci_scan_bridge_extend()
1324 * Disable Master-Abort Mode during probing to avoid reporting of in pci_scan_bridge_extend()
1355 child->primary = primary; in pci_scan_bridge_extend()
1357 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1360 buses = subordinate - secondary; in pci_scan_bridge_extend()
1363 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", in pci_scan_bridge_extend()
1366 /* Subordinate should equal child->busn_res.end */ in pci_scan_bridge_extend()
1367 if (subordinate > max) in pci_scan_bridge_extend()
1368 max = subordinate; in pci_scan_bridge_extend()
1399 next_busnr = max + 1; in pci_scan_bridge_extend()
1403 * This can happen when a bridge is hot-plugged, so in this in pci_scan_bridge_extend()
1404 * case we only re-scan this bus. in pci_scan_bridge_extend()
1412 bus->busn_res.end); in pci_scan_bridge_extend()
1414 max++; in pci_scan_bridge_extend()
1416 available_buses--; in pci_scan_bridge_extend()
1419 | ((unsigned int)(child->primary) << 0) in pci_scan_bridge_extend()
1420 | ((unsigned int)(child->busn_res.start) << 8) in pci_scan_bridge_extend()
1421 | ((unsigned int)(child->busn_res.end) << 16); in pci_scan_bridge_extend()
1436 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1437 max = pci_scan_child_bus_extend(child, available_buses); in pci_scan_bridge_extend()
1442 * cards with a PCI-to-PCI bridge can be inserted in pci_scan_bridge_extend()
1448 max+i+1)) in pci_scan_bridge_extend()
1450 while (parent->parent) { in pci_scan_bridge_extend()
1452 (parent->busn_res.end > max) && in pci_scan_bridge_extend()
1453 (parent->busn_res.end <= max+i)) { in pci_scan_bridge_extend()
1456 parent = parent->parent; in pci_scan_bridge_extend()
1462 * bridges -- try to leave one in pci_scan_bridge_extend()
1469 max += i; in pci_scan_bridge_extend()
1478 max = fixed_sub; in pci_scan_bridge_extend()
1479 pci_bus_update_busn_res_end(child, max); in pci_scan_bridge_extend()
1480 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); in pci_scan_bridge_extend()
1483 sprintf(child->name, in pci_scan_bridge_extend()
1484 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), in pci_scan_bridge_extend()
1485 pci_domain_nr(bus), child->number); in pci_scan_bridge_extend()
1488 while (bus->parent) { in pci_scan_bridge_extend()
1489 if ((child->busn_res.end > bus->busn_res.end) || in pci_scan_bridge_extend()
1490 (child->number > bus->busn_res.end) || in pci_scan_bridge_extend()
1491 (child->number < bus->number) || in pci_scan_bridge_extend()
1492 (child->busn_res.end < bus->number)) { in pci_scan_bridge_extend()
1493 …dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", in pci_scan_bridge_extend()
1494 &child->busn_res); in pci_scan_bridge_extend()
1497 bus = bus->parent; in pci_scan_bridge_extend()
1506 pm_runtime_put(&dev->dev); in pci_scan_bridge_extend()
1508 return max; in pci_scan_bridge_extend()
1512 * pci_scan_bridge() - Scan buses behind a bridge
1515 * @max: Starting subordinate number of buses behind this bridge
1523 * We need to process bridges in two passes -- first we scan those
1530 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) in pci_scan_bridge() argument
1532 return pci_scan_bridge_extend(bus, dev, max, 0, pass); in pci_scan_bridge()
1538 * The architecture-dependent code can tweak these, of course.
1545 if (dev->is_virtfn) { in pci_read_irq()
1546 dev->pin = 0; in pci_read_irq()
1547 dev->irq = 0; in pci_read_irq()
1552 dev->pin = irq; in pci_read_irq()
1555 dev->irq = irq; in pci_read_irq()
1570 pdev->pcie_cap = pos; in set_pcie_port_type()
1572 pdev->pcie_flags_reg = reg16; in set_pcie_port_type()
1573 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); in set_pcie_port_type()
1574 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); in set_pcie_port_type()
1578 pdev->link_active_reporting = 1; in set_pcie_port_type()
1598 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1599 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; in set_pcie_port_type()
1609 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1610 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; in set_pcie_port_type()
1621 pdev->is_hotplug_bridge = 1; in set_pcie_hotplug_bridge()
1631 dev->is_thunderbolt = 1; in set_pcie_thunderbolt()
1643 if (parent && (parent->untrusted || parent->external_facing)) in set_pcie_untrusted()
1644 dev->untrusted = true; in set_pcie_untrusted()
1663 (parent->external_facing || dev_is_removable(&parent->dev))) in pci_set_removable()
1664 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); in pci_set_removable()
1668 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1671 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1680 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1705 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1708 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1736 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to in pci_cfg_space_size()
1740 * the fact that the SR-IOV capability on the PF resides in extended in pci_cfg_space_size()
1741 * config space and must be accessible and non-aliased to have enabled in pci_cfg_space_size()
1745 if (dev->is_virtfn) in pci_cfg_space_size()
1749 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_cfg_space_size()
1752 class = dev->class >> 8; in pci_cfg_space_size()
1775 if (dev->is_virtfn) in pci_class()
1776 return dev->physfn->sriov->class; in pci_class()
1785 if (dev->is_virtfn) { in pci_subsystem_ids()
1786 *vendor = dev->physfn->sriov->subsystem_vendor; in pci_subsystem_ids()
1787 *device = dev->physfn->sriov->subsystem_device; in pci_subsystem_ids()
1800 if (dev->is_virtfn) in pci_hdr_type()
1801 return dev->physfn->sriov->hdr_type; in pci_hdr_type()
1810 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1814 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1828 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI in pci_intx_mask_broken()
1861 "PCIe to PCI/PCI-X bridge", in pci_type_str()
1862 "PCI/PCI-X to PCIe bridge", in pci_type_str()
1876 switch (dev->hdr_type) { in pci_type_str()
1889 * pci_setup_device - Fill in class and map information of a device
1893 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1909 dev->sysdata = dev->bus->sysdata; in pci_setup_device()
1910 dev->dev.parent = dev->bus->bridge; in pci_setup_device()
1911 dev->dev.bus = &pci_bus_type; in pci_setup_device()
1912 dev->hdr_type = hdr_type & 0x7f; in pci_setup_device()
1913 dev->multifunction = !!(hdr_type & 0x80); in pci_setup_device()
1914 dev->error_state = pci_channel_io_normal; in pci_setup_device()
1925 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) in pci_setup_device()
1928 dev->dma_mask = 0xffffffff; in pci_setup_device()
1930 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), in pci_setup_device()
1931 dev->bus->number, PCI_SLOT(dev->devfn), in pci_setup_device()
1932 PCI_FUNC(dev->devfn)); in pci_setup_device()
1936 dev->revision = class & 0xff; in pci_setup_device()
1937 dev->class = class >> 8; /* upper 3 bytes */ in pci_setup_device()
1942 /* Need to have dev->class ready */ in pci_setup_device()
1943 dev->cfg_size = pci_cfg_space_size(dev); in pci_setup_device()
1945 /* Need to have dev->cfg_size ready */ in pci_setup_device()
1951 dev->current_state = PCI_UNKNOWN; in pci_setup_device()
1958 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n", in pci_setup_device()
1959 dev->vendor, dev->device, dev->hdr_type, dev->class, in pci_setup_device()
1963 class = dev->class >> 8; in pci_setup_device()
1965 if (dev->non_compliant_bars && !dev->mmio_always_on) { in pci_setup_device()
1968 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); in pci_setup_device()
1975 dev->broken_intx_masking = pci_intx_mask_broken(dev); in pci_setup_device()
1977 switch (dev->hdr_type) { /* header type */ in pci_setup_device()
1984 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); in pci_setup_device()
1989 * addresses. These are not always echoed in BAR0-3, and in pci_setup_device()
1990 * BAR0-3 in a few cases contain junk! in pci_setup_device()
1998 res = &dev->resource[0]; in pci_setup_device()
1999 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
2000 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
2005 res = &dev->resource[1]; in pci_setup_device()
2006 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
2007 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
2014 res = &dev->resource[2]; in pci_setup_device()
2015 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
2016 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
2021 res = &dev->resource[3]; in pci_setup_device()
2022 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
2023 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
2032 * The PCI-to-PCI bridge spec requires that subtractive in pci_setup_device()
2037 dev->transparent = ((dev->class & 0xff) == 1); in pci_setup_device()
2043 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
2044 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); in pci_setup_device()
2053 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
2054 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
2058 pci_err(dev, "unknown header type %02x, ignoring device\n", in pci_setup_device()
2059 dev->hdr_type); in pci_setup_device()
2061 return -EIO; in pci_setup_device()
2064 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", in pci_setup_device()
2065 dev->class, dev->hdr_type); in pci_setup_device()
2066 dev->class = PCI_CLASS_NOT_DEFINED << 8; in pci_setup_device()
2081 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ in pci_configure_mps()
2082 if (dev->is_virtfn) in pci_configure_mps()
2093 mps = 128 << dev->pcie_mpss; in pci_configure_mps()
2096 …pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and repor… in pci_configure_mps()
2112 …pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_sa… in pci_configure_mps()
2124 mpss = 128 << dev->pcie_mpss; in pci_configure_mps()
2127 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", in pci_configure_mps()
2128 mpss, p_mps, 128 << bridge->pcie_mpss); in pci_configure_mps()
2134 …pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and repor… in pci_configure_mps()
2139 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", in pci_configure_mps()
2164 host = pci_find_host_bridge(dev->bus); in pci_configure_extended_tags()
2172 if (host->no_ext_tags) { in pci_configure_extended_tags()
2190 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2210 if (dev->is_virtfn) in pci_configure_relaxed_ordering()
2218 * Ports. Peer-to-Peer DMA is another can of worms. in pci_configure_relaxed_ordering()
2224 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { in pci_configure_relaxed_ordering()
2248 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2251 if (bridge && bridge->eetlp_prefix_path) in pci_configure_eetlp_prefix()
2252 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2261 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_configure_serr()
2297 * pci_release_dev - Free a PCI device structure when all users of it are
2312 pci_bus_put(pci_dev->bus); in pci_release_dev()
2313 kfree(pci_dev->driver_override); in pci_release_dev()
2314 bitmap_free(pci_dev->dma_alias_mask); in pci_release_dev()
2331 INIT_LIST_HEAD(&dev->bus_list); in pci_alloc_dev()
2332 dev->dev.type = &pci_dev_type; in pci_alloc_dev()
2333 dev->bus = pci_bus_get(bus); in pci_alloc_dev()
2334 dev->driver_exclusive_resource = (struct resource) { in pci_alloc_dev()
2337 .end = -1, in pci_alloc_dev()
2340 spin_lock_init(&dev->pcie_cap_lock); in pci_alloc_dev()
2342 raw_spin_lock_init(&dev->msi_lock); in pci_alloc_dev()
2366 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", in pci_bus_wait_rrs()
2367 pci_domain_nr(bus), bus->number, in pci_bus_wait_rrs()
2368 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_rrs()
2373 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", in pci_bus_wait_rrs()
2374 pci_domain_nr(bus), bus->number, in pci_bus_wait_rrs()
2375 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_rrs()
2385 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", in pci_bus_wait_rrs()
2386 pci_domain_nr(bus), bus->number, in pci_bus_wait_rrs()
2387 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_rrs()
2413 struct pci_dev *bridge = bus->self; in pci_bus_read_dev_vendor_id()
2419 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && in pci_bus_read_dev_vendor_id()
2420 bridge->device == 0x80b5) in pci_bus_read_dev_vendor_id()
2429 * Read the config data for a PCI device, sanity-check it,
2444 dev->devfn = devfn; in pci_scan_device()
2445 dev->vendor = l & 0xffff; in pci_scan_device()
2446 dev->device = (l >> 16) & 0xffff; in pci_scan_device()
2449 pci_bus_put(dev->bus); in pci_scan_device()
2468 /* Multi-function PCIe devices share the same link/status */ in pcie_report_downtraining()
2469 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) in pcie_report_downtraining()
2480 pci_msix_init(dev); /* Disable MSI-X */ in pci_init_capabilities()
2482 /* Buffers for saving PCIe and PCI-X capabilities */ in pci_init_capabilities()
2487 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ in pci_init_capabilities()
2506 * per-device basis should be called from here.
2516 d = dev_get_msi_domain(&dev->dev); in pci_dev_msi_domain()
2537 * device-specific MSI domain, then inherit the default domain in pci_set_msi_domain()
2542 d = dev_get_msi_domain(&dev->bus->dev); in pci_set_msi_domain()
2544 dev_set_msi_domain(&dev->dev, d); in pci_set_msi_domain()
2553 device_initialize(&dev->dev); in pci_device_add()
2554 dev->dev.release = pci_release_dev; in pci_device_add()
2556 set_dev_node(&dev->dev, pcibus_to_node(bus)); in pci_device_add()
2557 dev->dev.dma_mask = &dev->dma_mask; in pci_device_add()
2558 dev->dev.dma_parms = &dev->dma_parms; in pci_device_add()
2559 dev->dev.coherent_dma_mask = 0xffffffffull; in pci_device_add()
2561 dma_set_max_seg_size(&dev->dev, 65536); in pci_device_add()
2562 dma_set_seg_boundary(&dev->dev, 0xffffffff); in pci_device_add()
2571 dev->state_saved = false; in pci_device_add()
2580 list_add_tail(&dev->bus_list, &bus->devices); in pci_device_add()
2590 dev->match_driver = false; in pci_device_add()
2591 ret = device_add(&dev->dev); in pci_device_add()
2624 return -ENODEV; in next_ari_fn()
2628 return -ENODEV; in next_ari_fn()
2633 return -ENODEV; /* protect against malformed list */ in next_ari_fn()
2644 return -ENODEV; in next_fn()
2646 if (dev && !dev->multifunction) in next_fn()
2647 return -ENODEV; in next_fn()
2654 struct pci_dev *bridge = bus->self; in only_one_child()
2675 * pci_scan_slot - Scan a PCI slot on a bus for devices
2680 * discovered devices to the @bus->devices list. New devices
2699 dev->multifunction = 1; in pci_scan_slot()
2713 if (bus->self && nr) in pci_scan_slot()
2714 pcie_aspm_init_link_state(bus->self); in pci_scan_slot()
2729 * drivers attached. A hot-added device might support only the minimum in pcie_find_smpss()
2731 * where devices may be hot-added, we limit the fabric MPS to 128 so in pcie_find_smpss()
2732 * hot-added devices will work correctly. in pcie_find_smpss()
2734 * However, if we hot-add a device to a slot directly below a Root in pcie_find_smpss()
2737 * reconfigure MPS on both the Root Port and the hot-added device, in pcie_find_smpss()
2740 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. in pcie_find_smpss()
2742 if (dev->is_hotplug_bridge && in pcie_find_smpss()
2746 if (*smpss > dev->pcie_mpss) in pcie_find_smpss()
2747 *smpss = dev->pcie_mpss; in pcie_find_smpss()
2757 mps = 128 << dev->pcie_mpss; in pcie_write_mps()
2760 dev->bus->self) in pcie_write_mps()
2775 mps = min(mps, pcie_get_mps(dev->bus->self)); in pcie_write_mps()
2795 * For max performance, the MRRS must be set to the largest supported in pcie_write_mrrs()
2838 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", in pcie_bus_configure_set()
2839 pcie_get_mps(dev), 128 << dev->pcie_mpss, in pcie_bus_configure_set()
2846 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2854 if (!bus->self) in pcie_bus_configure_settings()
2857 if (!pci_is_pcie(bus->self)) in pcie_bus_configure_settings()
2861 * FIXME - Peer to peer DMA is possible, though the endpoint would need in pcie_bus_configure_settings()
2869 smpss = bus->self->pcie_mpss; in pcie_bus_configure_settings()
2871 pcie_find_smpss(bus->self, &smpss); in pcie_bus_configure_settings()
2875 pcie_bus_configure_set(bus->self, &smpss); in pcie_bus_configure_settings()
2890 * pci_scan_child_bus_extend() - Scan devices below a bus
2898 * equally between hotplug-capable bridges to allow future extension of the
2905 unsigned int start = bus->busn_res.start; in pci_scan_child_bus_extend()
2906 unsigned int devfn, cmax, max = start; in pci_scan_child_bus_extend() local
2909 dev_dbg(&bus->dev, "scanning bus\n"); in pci_scan_child_bus_extend()
2915 /* Reserve buses for SR-IOV capability */ in pci_scan_child_bus_extend()
2917 max += used_buses; in pci_scan_child_bus_extend()
2920 * After performing arch-dependent fixup of the bus, look behind in pci_scan_child_bus_extend()
2921 * all PCI-to-PCI bridges on this bus. in pci_scan_child_bus_extend()
2923 if (!bus->is_added) { in pci_scan_child_bus_extend()
2924 dev_dbg(&bus->dev, "fixups for bus\n"); in pci_scan_child_bus_extend()
2926 bus->is_added = 1; in pci_scan_child_bus_extend()
2935 if (dev->is_hotplug_bridge) in pci_scan_child_bus_extend()
2947 cmax = max; in pci_scan_child_bus_extend()
2948 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); in pci_scan_child_bus_extend()
2955 if (max - cmax > 1) in pci_scan_child_bus_extend()
2956 used_buses += max - cmax - 1; in pci_scan_child_bus_extend()
2971 } else if (dev->is_hotplug_bridge) { in pci_scan_child_bus_extend()
2977 buses = min(buses, available_buses - used_buses + 1); in pci_scan_child_bus_extend()
2980 cmax = max; in pci_scan_child_bus_extend()
2981 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); in pci_scan_child_bus_extend()
2983 if (max - cmax > 1) in pci_scan_child_bus_extend()
2984 used_buses += max - cmax - 1; in pci_scan_child_bus_extend()
2992 if (bus->self && bus->self->is_hotplug_bridge) { in pci_scan_child_bus_extend()
2994 pci_hotplug_bus_size - 1); in pci_scan_child_bus_extend()
2995 if (max - start < used_buses) { in pci_scan_child_bus_extend()
2996 max = start + used_buses; in pci_scan_child_bus_extend()
2999 if (max > bus->busn_res.end) in pci_scan_child_bus_extend()
3000 max = bus->busn_res.end; in pci_scan_child_bus_extend()
3002 dev_dbg(&bus->dev, "%pR extended by %#02x\n", in pci_scan_child_bus_extend()
3003 &bus->busn_res, max - start); in pci_scan_child_bus_extend()
3012 * Return how far we've got finding sub-buses. in pci_scan_child_bus_extend()
3014 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); in pci_scan_child_bus_extend()
3015 return max; in pci_scan_child_bus_extend()
3019 * pci_scan_child_bus() - Scan devices below a bus
3032 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3035 * Default empty implementation. Replace with an architecture-specific setup
3061 bridge->dev.parent = parent; in pci_create_root_bus()
3063 list_splice_init(resources, &bridge->windows); in pci_create_root_bus()
3064 bridge->sysdata = sysdata; in pci_create_root_bus()
3065 bridge->busnr = bus; in pci_create_root_bus()
3066 bridge->ops = ops; in pci_create_root_bus()
3072 return bridge->bus; in pci_create_root_bus()
3075 put_device(&bridge->dev); in pci_create_root_bus()
3089 dev_err(bridge->dev.parent, "Scanning root bridge failed"); in pci_host_probe()
3093 bus = bridge->bus; in pci_host_probe()
3096 if (bridge->preserve_config) in pci_host_probe()
3105 list_for_each_entry(child, &bus->children, node) in pci_host_probe()
3117 struct resource *res = &b->busn_res; in pci_bus_insert_busn_res()
3120 res->start = bus; in pci_bus_insert_busn_res()
3121 res->end = bus_max; in pci_bus_insert_busn_res()
3122 res->flags = IORESOURCE_BUS; in pci_bus_insert_busn_res()
3125 parent_res = &b->parent->busn_res; in pci_bus_insert_busn_res()
3128 res->flags |= IORESOURCE_PCI_FIXED; in pci_bus_insert_busn_res()
3134 dev_info(&b->dev, in pci_bus_insert_busn_res()
3137 parent_res, conflict->name, conflict); in pci_bus_insert_busn_res()
3144 struct resource *res = &b->busn_res; in pci_bus_update_busn_res_end()
3149 if (res->start > bus_max) in pci_bus_update_busn_res_end()
3150 return -EINVAL; in pci_bus_update_busn_res_end()
3152 size = bus_max - res->start + 1; in pci_bus_update_busn_res_end()
3153 ret = adjust_resource(res, res->start, size); in pci_bus_update_busn_res_end()
3154 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", in pci_bus_update_busn_res_end()
3157 if (!ret && !res->parent) in pci_bus_update_busn_res_end()
3158 pci_bus_insert_busn_res(b, res->start, res->end); in pci_bus_update_busn_res_end()
3165 struct resource *res = &b->busn_res; in pci_bus_release_busn_res()
3168 if (!res->flags || !res->parent) in pci_bus_release_busn_res()
3172 dev_info(&b->dev, "busn_res: %pR %s released\n", in pci_bus_release_busn_res()
3181 int max, bus, ret; in pci_scan_root_bus_bridge() local
3184 return -EINVAL; in pci_scan_root_bus_bridge()
3186 resource_list_for_each_entry(window, &bridge->windows) in pci_scan_root_bus_bridge()
3187 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus_bridge()
3188 bridge->busnr = window->res->start; in pci_scan_root_bus_bridge()
3197 b = bridge->bus; in pci_scan_root_bus_bridge()
3198 bus = bridge->busnr; in pci_scan_root_bus_bridge()
3201 dev_info(&b->dev, in pci_scan_root_bus_bridge()
3202 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus_bridge()
3207 max = pci_scan_child_bus(b); in pci_scan_root_bus_bridge()
3210 pci_bus_update_busn_res_end(b, max); in pci_scan_root_bus_bridge()
3222 int max; in pci_scan_root_bus() local
3225 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus()
3235 dev_info(&b->dev, in pci_scan_root_bus()
3236 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus()
3241 max = pci_scan_child_bus(b); in pci_scan_root_bus()
3244 pci_bus_update_busn_res_end(b, max); in pci_scan_root_bus()
3270 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3278 * Returns the max number of subordinate bus discovered.
3282 unsigned int max; in pci_rescan_bus_bridge_resize() local
3283 struct pci_bus *bus = bridge->subordinate; in pci_rescan_bus_bridge_resize()
3285 max = pci_scan_child_bus(bus); in pci_rescan_bus_bridge_resize()
3291 return max; in pci_rescan_bus_bridge_resize()
3295 * pci_rescan_bus - Scan a PCI bus for devices
3301 * Returns the max number of subordinate bus discovered.
3305 unsigned int max; in pci_rescan_bus() local
3307 max = pci_scan_child_bus(bus); in pci_rescan_bus()
3311 return max; in pci_rescan_bus()
3339 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; in pci_sort_bf_cmp()
3340 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; in pci_sort_bf_cmp()
3342 if (a->bus->number < b->bus->number) return -1; in pci_sort_bf_cmp()
3343 else if (a->bus->number > b->bus->number) return 1; in pci_sort_bf_cmp()
3345 if (a->devfn < b->devfn) return -1; in pci_sort_bf_cmp()
3346 else if (a->devfn > b->devfn) return 1; in pci_sort_bf_cmp()
3358 struct pci_bus *parent = dev->bus; in pci_hp_add_bridge()
3359 int busnr, start = parent->busn_res.start; in pci_hp_add_bridge()
3361 int end = parent->busn_res.end; in pci_hp_add_bridge()
3367 if (busnr-- > end) { in pci_hp_add_bridge()
3368 pci_err(dev, "No bus number available for hot-added bridge\n"); in pci_hp_add_bridge()
3369 return -1; in pci_hp_add_bridge()
3376 * Distribute the available bus numbers between hotplug-capable in pci_hp_add_bridge()
3379 available_buses = end - busnr; in pci_hp_add_bridge()
3384 if (!dev->subordinate) in pci_hp_add_bridge()
3385 return -1; in pci_hp_add_bridge()