Lines Matching full:upstream

114 	 * on the downstream component before the upstream. So, don't attempt to  in pci_restore_aspm_l1ss_state()
148 * by the upstream in pci_restore_aspm_l1ss_state()
195 #define PCIE_LINK_STATE_L0S_UP BIT(0) /* Upstream direction L0s state */
208 struct pci_dev *pdev; /* Upstream component of the Link */
405 /* Check upstream component if bit Slot Clock Configuration is 1 */ in pcie_aspm_configure_common_clock()
438 /* Configure upstream component */ in pcie_aspm_configure_common_clock()
582 /* Check upstream direction L0s latency */ in pcie_aspm_check_latency()
690 /* Program Common_Mode_Restore_Time in upstream device */ in aspm_calc_l12_info()
798 * Re-read upstream/downstream components' register state after in pcie_aspm_cap_init()
910 u32 upstream = 0, dwstream = 0; in pcie_config_aspm_link() local
930 /* Convert ASPM state to upstream/downstream ASPM register state */ in pcie_config_aspm_link()
934 upstream |= PCI_EXP_LNKCTL_ASPM_L0S; in pcie_config_aspm_link()
936 upstream |= PCI_EXP_LNKCTL_ASPM_L1; in pcie_config_aspm_link()
946 * upstream component first and then downstream, and vice in pcie_config_aspm_link()
950 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
954 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
1080 * We allocate pcie_link_state for the component on the upstream in pcie_aspm_init_link_state()
1102 * upstream links also because capable state of them can be in pcie_aspm_init_link_state()
1192 * disabled in the upstream bridge, so re-enable it before enabling in pci_configure_ltr()
1259 /* Recheck latencies and configure upstream links */ in pcie_aspm_exit_link_state()
1519 * Relies on the upstream bridge's link_state being valid. The link_state