Lines Matching +full:min +full:- +full:wakeup +full:- +full:pin +full:- +full:assert +full:- +full:time +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
83 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); in pci_dev_d3_sleep()
87 /* Use a 20% upper bound, 1ms minimum */ in pci_dev_d3_sleep()
96 return dev->reset_methods[0] != 0; in pci_reset_supported()
115 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
126 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
143 * measured in 32-bit words, not bytes.
185 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
196 max = bus->busn_res.end; in pci_bus_max_busnr()
197 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
207 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
219 return -EIO; in pci_status_get_and_clear_errors()
233 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
234 resource_size_t start = res->start; in __pci_ioremap_resource()
240 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
265 * pci_dev_str_match_path - test if a path string matches a device
276 * A path for a device can be obtained using 'lspci -t'. Using a path
293 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
295 return -ENOMEM; in pci_dev_str_match_path()
303 ret = -EINVAL; in pci_dev_str_match_path()
307 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
333 ret = -EINVAL; in pci_dev_str_match_path()
338 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
339 bus == dev->bus->number && in pci_dev_str_match_path()
340 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
348 * pci_dev_str_match - test if a string matches a device
365 * through the use of 'lspci -t'.
370 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
392 return -EINVAL; in pci_dev_str_match()
400 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
401 (!device || device == dev->device) && in pci_dev_str_match()
403 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
405 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
435 while ((*ttl)--) { in __pci_find_next_cap_ttl()
461 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
487 * pci_find_capability - query for devices' capabilities
502 * %PCI_CAP_ID_PCIX PCI-X
509 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
511 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
518 * pci_bus_find_capability - query for devices' capabilities
545 * pci_find_next_ext_capability - Find an extended capability
553 * vendor-specific capability, and this provides a way to find them all.
562 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
564 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
580 while (ttl-- > 0) { in pci_find_next_ext_capability()
597 * pci_find_ext_capability - Find an extended capability
617 * pci_get_dsn - Read and return the 8-byte Device Serial Number
660 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
670 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
679 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
698 * pci_find_ht_capability - query a device's HyperTransport capabilities
712 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
721 * pci_find_vsec_capability - Find a vendor-specific extended capability
724 * @cap: Vendor-specific capability ID
736 if (vendor != dev->vendor) in pci_find_vsec_capability()
754 * pci_find_dvsec_capability - Find DVSEC for vendor
757 * @dvsec: Designated Vendor-specific capability ID
786 * pci_find_parent_resource - return resource region of parent bus of given
797 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
809 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
810 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
815 * be both a positively-decoded aperture and a in pci_find_parent_resource()
816 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
817 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
829 * pci_find_resource - Return matching PCI device resource
842 struct resource *r = &dev->resource[i]; in pci_find_resource()
844 if (r->start && resource_contains(r, res)) in pci_find_resource()
853 * pci_resource_name - Return the name of the PCI resource
902 if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS && in pci_resource_name()
913 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
928 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
941 * pci_request_acs - ask for ACS to be enabled if supported
974 end = delimit - p - 1; in __pci_config_acs()
976 while (end > -1) { in __pci_config_acs()
980 end--; in __pci_config_acs()
985 end--; in __pci_config_acs()
988 end--; in __pci_config_acs()
1033 caps->ctrl = (caps->ctrl & ~mask) | (caps->fw_ctrl & mask); in __pci_config_acs()
1034 caps->ctrl |= flags; in __pci_config_acs()
1036 pci_info(dev, "Configured ACS to %#06x\n", caps->ctrl); in __pci_config_acs()
1040 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
1047 caps->ctrl |= (caps->cap & PCI_ACS_SV); in pci_std_enable_acs()
1050 caps->ctrl |= (caps->cap & PCI_ACS_RR); in pci_std_enable_acs()
1053 caps->ctrl |= (caps->cap & PCI_ACS_CR); in pci_std_enable_acs()
1056 caps->ctrl |= (caps->cap & PCI_ACS_UF); in pci_std_enable_acs()
1059 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
1060 caps->ctrl |= (caps->cap & PCI_ACS_TB); in pci_std_enable_acs()
1064 * pci_enable_acs - enable ACS if hardware support it
1079 pos = dev->acs_cap; in pci_enable_acs()
1103 * pcie_read_tlp_log - read TLP Header Log
1121 &tlp_log->dw[i]); in pcie_read_tlp_log()
1131 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1209 * pci_update_current_state - Read power state of given device and cache it
1223 dev->current_state = PCI_D3cold; in pci_update_current_state()
1224 } else if (dev->pm_cap) { in pci_update_current_state()
1227 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1229 dev->current_state = PCI_D3cold; in pci_update_current_state()
1232 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_update_current_state()
1234 dev->current_state = state; in pci_update_current_state()
1239 * pci_refresh_power_state - Refresh the given device's power state data
1248 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1252 * pci_platform_power_transition - Use platform to change device power state
1263 else if (!dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1264 dev->current_state = PCI_D0; in pci_platform_power_transition()
1272 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1277 * pci_resume_bus - Walk given bus and runtime resume devices on it
1303 * with Request Retry Status (RRS) if it needs more time to in pci_dev_wait()
1309 * Vendor ID until we get non-RRS status. in pci_dev_wait()
1316 * ID for VFs and non-existent devices also returns ~0, so read the in pci_dev_wait()
1324 return -ENOTTY; in pci_dev_wait()
1327 if (root && root->config_rrs_sv) { in pci_dev_wait()
1339 delay - 1, reset_type); in pci_dev_wait()
1340 return -ENOTTY; in pci_dev_wait()
1352 delay - 1, reset_type); in pci_dev_wait()
1360 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1363 pci_dbg(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1370 * pci_power_up - Put the given device into D0
1378 * put the device in D0 via non-PCI means.
1388 if (!dev->pm_cap) { in pci_power_up()
1391 dev->current_state = PCI_D0; in pci_power_up()
1393 dev->current_state = state; in pci_power_up()
1395 return -EIO; in pci_power_up()
1398 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_power_up()
1401 pci_power_name(dev->current_state)); in pci_power_up()
1402 dev->current_state = PCI_D3cold; in pci_power_up()
1403 return -EIO; in pci_power_up()
1408 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) && in pci_power_up()
1418 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); in pci_power_up()
1427 dev->current_state = PCI_D0; in pci_power_up()
1435 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1454 if (dev->current_state == PCI_D0) in pci_set_full_power_state()
1460 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_full_power_state()
1461 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_full_power_state()
1462 if (dev->current_state != PCI_D0) { in pci_set_full_power_state()
1464 pci_power_name(dev->current_state)); in pci_set_full_power_state()
1482 if (dev->bus->self) in pci_set_full_power_state()
1483 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_full_power_state()
1489 * __pci_dev_set_current_state - Set current state of a PCI device
1497 dev->current_state = state; in __pci_dev_set_current_state()
1502 * pci_bus_set_current_state - Walk given bus and set current state of devices
1524 * pci_set_low_power_state - Put a PCI device into a low-power state.
1529 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1532 * -EINVAL if the requested state is invalid.
1533 * -EIO if device does not support PCI PM or its PM capabilities register has a
1542 if (!dev->pm_cap) in pci_set_low_power_state()
1543 return -EIO; in pci_set_low_power_state()
1547 * we're already in a low-power state, we can only go deeper. E.g., in pci_set_low_power_state()
1551 if (dev->current_state <= PCI_D3cold && dev->current_state > state) { in pci_set_low_power_state()
1553 pci_power_name(dev->current_state), in pci_set_low_power_state()
1555 return -EINVAL; in pci_set_low_power_state()
1559 if ((state == PCI_D1 && !dev->d1_support) in pci_set_low_power_state()
1560 || (state == PCI_D2 && !dev->d2_support)) in pci_set_low_power_state()
1561 return -EIO; in pci_set_low_power_state()
1563 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1566 pci_power_name(dev->current_state), in pci_set_low_power_state()
1568 dev->current_state = PCI_D3cold; in pci_set_low_power_state()
1569 return -EIO; in pci_set_low_power_state()
1576 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_set_low_power_state()
1584 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1585 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_low_power_state()
1586 if (dev->current_state != state) in pci_set_low_power_state()
1588 pci_power_name(dev->current_state), in pci_set_low_power_state()
1591 if (dev->bus->self) in pci_set_low_power_state()
1592 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_low_power_state()
1617 if (dev->current_state == state) in __pci_set_power_state()
1627 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in __pci_set_power_state()
1641 if (dev->current_state == PCI_D3cold) in __pci_set_power_state()
1642 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold, locked); in __pci_set_power_state()
1654 * pci_set_power_state - Set the power state of a PCI device
1662 * -EINVAL if the requested state is invalid.
1663 * -EIO if device does not support PCI PM or its PM capabilities register has a
1691 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1692 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1720 return -ENOMEM; in pci_save_pcie_state()
1723 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1757 * Check and re-configure the bit here before restoring device. in pci_restore_pcie_state()
1762 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1784 return -ENOMEM; in pci_save_pcix_state()
1788 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1803 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1809 * pci_save_state - save the PCI configuration space of a device before
1818 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1820 i * 4, dev->saved_config_space[i]); in pci_save_state()
1822 dev->state_saved = true; in pci_save_state()
1849 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n", in pci_restore_config_dword()
1852 if (retry-- <= 0) in pci_restore_config_dword()
1869 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1871 pdev->saved_config_space[index], in pci_restore_config_space_range()
1877 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1882 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1915 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1924 * pci_restore_state - Restore the saved state of a PCI device
1929 if (!dev->state_saved) in pci_restore_state()
1953 dev->state_saved = false; in pci_restore_state()
1963 * pci_store_saved_state - Allocate and return an opaque struct containing
1976 if (!dev->state_saved) in pci_store_saved_state()
1981 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1982 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1988 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1989 sizeof(state->config_space)); in pci_store_saved_state()
1991 cap = state->cap; in pci_store_saved_state()
1992 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1993 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1994 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
2004 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
2013 dev->state_saved = false; in pci_load_saved_state()
2018 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
2019 sizeof(state->config_space)); in pci_load_saved_state()
2021 cap = state->cap; in pci_load_saved_state()
2022 while (cap->size) { in pci_load_saved_state()
2025 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
2026 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
2027 return -EINVAL; in pci_load_saved_state()
2029 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
2031 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
2034 dev->state_saved = true; in pci_load_saved_state()
2040 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
2065 u8 pin; in do_pci_enable_device() local
2068 if (err < 0 && err != -EIO) in do_pci_enable_device()
2080 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
2083 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in do_pci_enable_device()
2084 if (pin) { in do_pci_enable_device()
2095 * pci_reenable_device - Resume abandoned device
2104 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
2119 if (!dev->is_busmaster) in pci_enable_bridge()
2141 * (e.g. if the device really is in D0 at enable time). in pci_enable_device_flags()
2143 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
2145 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
2154 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2157 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2162 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
2167 * pci_enable_device_mem - Initialize a device for use with Memory space
2170 * Initialize device before it's used by a driver. Ask low-level code
2181 * pci_enable_device - Initialize device before it's used by a driver.
2184 * Initialize device before it's used by a driver. Ask low-level code
2198 * pcibios_device_add - provide arch specific hooks when adding device dev
2211 * pcibios_release_device - provide arch specific hooks when releasing
2222 * pcibios_disable_device - disable arch specific PCI resources for device dev
2245 * pci_disable_enabled_device - Disable device without updating enable_cnt
2258 * pci_disable_device - Disable PCI device after use
2262 * anymore. This only involves disabling PCI bus-mastering, if active.
2269 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2270 "disabling already-disabled device"); in pci_disable_device()
2272 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2277 dev->is_busmaster = 0; in pci_disable_device()
2282 * pcibios_set_pcie_reset_state - set reset state for device dev
2292 return -EINVAL; in pcibios_set_pcie_reset_state()
2296 * pci_set_pcie_reset_state - set reset state for device dev
2319 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2328 * pci_check_pme_status - Check if given device has generated PME.
2341 if (!dev->pm_cap) in pci_check_pme_status()
2344 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2363 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2372 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2373 dev->pme_poll = false; in pci_pme_wakeup()
2377 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2383 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2394 * pci_pme_capable - check the capability of PCI device to generate PME#
2400 if (!dev->pm_cap) in pci_pme_capable()
2403 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2413 struct pci_dev *pdev = pme_dev->dev; in pci_pme_list_scan()
2415 if (pdev->pme_poll) { in pci_pme_list_scan()
2416 struct pci_dev *bridge = pdev->bus->self; in pci_pme_list_scan()
2417 struct device *dev = &pdev->dev; in pci_pme_list_scan()
2418 struct device *bdev = bridge ? &bridge->dev : NULL; in pci_pme_list_scan()
2432 if (bridge->current_state != PCI_D0) in pci_pme_list_scan()
2442 pdev->current_state != PCI_D3cold) in pci_pme_list_scan()
2449 list_del(&pme_dev->list); in pci_pme_list_scan()
2463 if (!dev->pme_support) in __pci_pme_active()
2466 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2472 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2476 * pci_pme_restore - Restore PME configuration after config space restore.
2483 if (!dev->pme_support) in pci_pme_restore()
2486 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2487 if (dev->wakeup_prepared) { in pci_pme_restore()
2494 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2498 * pci_pme_active - enable or disable PCI device's PME# function
2520 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2529 if (dev->pme_poll) { in pci_pme_active()
2538 pme_dev->dev = dev; in pci_pme_active()
2540 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2549 if (pme_dev->dev == dev) { in pci_pme_active()
2550 list_del(&pme_dev->list); in pci_pme_active()
2564 * __pci_enable_wake - enable PCI device as wakeup event source
2566 * @state: PCI state from which device will issue wakeup events
2569 * This enables the device as a wakeup event source, or disables it.
2570 * When such events involves platform-specific hooks, those hooks are
2578 * -EINVAL is returned if device is not supposed to wake up the system
2580 * the native mechanism fail to enable the generation of wake-up events
2587 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2588 * wakeup on behalf of subordinate devices which is set up in __pci_enable_wake()
2590 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2597 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2603 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2624 dev->wakeup_prepared = true; in __pci_enable_wake()
2628 dev->wakeup_prepared = false; in __pci_enable_wake()
2635 * pci_enable_wake - change wakeup settings for a PCI device
2637 * @state: PCI state from which device will issue wakeup events
2645 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2646 return -EINVAL; in pci_enable_wake()
2653 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2655 * @enable: True to enable wake-up event generation; false to disable
2658 * and this function allows them to set that up cleanly - pci_enable_wake()
2659 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2664 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2675 * pci_target_state - find an appropriate low power state for a given PCI dev
2677 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2683 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) in pci_target_state() argument
2706 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2707 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2710 if (dev->current_state == PCI_D3cold) in pci_target_state()
2712 else if (!dev->pm_cap) in pci_target_state()
2715 if (wakeup && dev->pme_support) { in pci_target_state()
2722 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2723 state--; in pci_target_state()
2727 else if (dev->pme_support & 1) in pci_target_state()
2735 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2745 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep() local
2746 pci_power_t target_state = pci_target_state(dev, wakeup); in pci_prepare_to_sleep()
2750 return -EIO; in pci_prepare_to_sleep()
2752 pci_enable_wake(dev, target_state, wakeup); in pci_prepare_to_sleep()
2764 * pci_back_from_sleep - turn PCI device on during system-wide transition
2768 * Disable device's system wake-up capability and put it into D0.
2783 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2786 * Prepare @dev to generate wake-up events at run time and put it into a low
2794 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2796 return -EIO; in pci_finish_runtime_suspend()
2809 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2812 * Return true if the device itself is capable of generating wake-up events
2814 * PME and one of its upstream bridges can generate wake-up events.
2818 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2820 if (!dev->pme_support) in pci_dev_run_wake()
2823 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2827 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2830 while (bus->parent) { in pci_dev_run_wake()
2831 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2833 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2836 bus = bus->parent; in pci_dev_run_wake()
2840 if (bus->bridge) in pci_dev_run_wake()
2841 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2848 * pci_dev_need_resume - Check if it is necessary to resume the device.
2851 * Return 'true' if the device is not runtime-suspended or it has to be
2852 * reconfigured due to wakeup settings difference between system and runtime
2854 * (system-wide) transition.
2858 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2871 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2873 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2877 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2880 * If the device is suspended and it is not configured for system wakeup,
2889 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2891 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2894 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2897 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2901 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2904 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2906 * the device was not configured for system wakeup.
2910 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2915 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2917 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2920 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2924 * pci_choose_state - Choose the power state of a PCI device.
2941 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2942 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2948 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
2957 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
2963 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
2964 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2980 .ident = "X299 DESIGNARE EX-CF",
2983 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3001 * https://gitlab.freedesktop.org/drm/amd/-/issues/3229
3003 .ident = "Hewlett-Packard HP Pavilion 17 Notebook PC/1972",
3005 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
3015 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3035 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
3037 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
3044 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
3056 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
3079 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
3081 /* ... and if it is wakeup capable to do so from D3cold. */ in pci_dev_check_d3cold()
3082 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
3094 * pci_bridge_d3_update - Update bridge D3 capabilities
3103 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
3115 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3135 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3136 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3139 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3140 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3147 * pci_d3cold_enable - Enable D3cold for device
3156 if (dev->no_d3cold) { in pci_d3cold_enable()
3157 dev->no_d3cold = false; in pci_d3cold_enable()
3164 * pci_d3cold_disable - Disable D3cold for device
3173 if (!dev->no_d3cold) { in pci_d3cold_disable()
3174 dev->no_d3cold = true; in pci_d3cold_disable()
3181 * pci_pm_init - Initialize PM functions of given PCI device
3190 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3191 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3192 pm_runtime_enable(&dev->dev); in pci_pm_init()
3193 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3194 dev->wakeup_prepared = false; in pci_pm_init()
3196 dev->pm_cap = 0; in pci_pm_init()
3197 dev->pme_support = 0; in pci_pm_init()
3212 dev->pm_cap = pm; in pci_pm_init()
3213 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3214 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3215 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3216 dev->d3cold_allowed = true; in pci_pm_init()
3218 dev->d1_support = false; in pci_pm_init()
3219 dev->d2_support = false; in pci_pm_init()
3222 dev->d1_support = true; in pci_pm_init()
3224 dev->d2_support = true; in pci_pm_init()
3226 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3228 dev->d1_support ? " D1" : "", in pci_pm_init()
3229 dev->d2_support ? " D2" : ""); in pci_pm_init()
3240 dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc); in pci_pm_init()
3241 dev->pme_poll = true; in pci_pm_init()
3243 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3246 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3253 dev->imm_ready = 1; in pci_pm_init()
3283 return &dev->resource[bei]; in pci_ea_get_resource()
3287 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3288 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3291 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3351 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3360 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3370 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3392 if (ent_size != ent_offset - offset) { in pci_ea_read()
3394 ent_size, ent_offset - offset); in pci_ea_read()
3398 res->name = pci_name(dev); in pci_ea_read()
3399 res->start = start; in pci_ea_read()
3400 res->end = end; in pci_ea_read()
3401 res->flags = flags; in pci_ea_read()
3434 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3441 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3452 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3456 * _pci_add_cap_save_buffer - allocate buffer for saving given
3479 return -ENOMEM; in _pci_add_cap_save_buffer()
3481 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3482 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3483 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3500 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3514 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3529 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3534 * pci_configure_ari - enable or disable ARI forwarding
3545 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3548 bridge = dev->bus->self; in pci_configure_ari()
3559 bridge->ari_enabled = 1; in pci_configure_ari()
3563 bridge->ari_enabled = 0; in pci_configure_ari()
3572 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3579 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3589 * pci_acs_enabled - test ACS against required flags for a given device
3599 * opportunity for peer-to-peer access. We therefore return 'true'
3613 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3622 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3624 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3638 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3639 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3646 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3655 if (!pdev->multifunction) in pci_acs_enabled()
3669 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3688 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3691 parent = pdev->bus->self; in pci_acs_path_enabled()
3698 * pci_acs_init - Initialize ACS if hardware supports it
3703 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3715 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3720 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3721 * Returns -ENOENT if no ctrl register for the BAR could be found.
3730 return -ENOTSUPP; in pci_rebar_find_pos()
3744 return -ENOENT; in pci_rebar_find_pos()
3748 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3768 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3777 * pci_rebar_get_current_size - get the current size of a BAR
3798 * pci_rebar_set_size - set a new size for a BAR
3823 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3832 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3837 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3846 if (dev->is_virtfn) in pci_enable_atomic_ops_to_root()
3847 return -EINVAL; in pci_enable_atomic_ops_to_root()
3850 return -EINVAL; in pci_enable_atomic_ops_to_root()
3856 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3865 return -EINVAL; in pci_enable_atomic_ops_to_root()
3868 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3869 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3878 return -EINVAL; in pci_enable_atomic_ops_to_root()
3884 return -EINVAL; in pci_enable_atomic_ops_to_root()
3893 return -EINVAL; in pci_enable_atomic_ops_to_root()
3896 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3906 * pci_release_region - Release a PCI bar
3939 * __pci_request_region - Reserved PCI I/O and memory resource
3987 &pdev->resource[bar]); in __pci_request_region()
3988 return -EBUSY; in __pci_request_region()
3992 * pci_request_region - Reserve PCI I/O and memory resource
4019 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4048 while (--i >= 0) in __pci_request_selected_regions()
4052 return -EBUSY; in __pci_request_selected_regions()
4057 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4077 * pci_request_selected_regions_exclusive - Request regions exclusively
4098 * pci_release_regions - Release reserved PCI I/O and memory resources
4108 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4113 * pci_request_regions - Reserve PCI I/O and memory resources
4133 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions()
4138 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4162 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions_exclusive()
4178 return -EINVAL; in pci_register_io_range()
4182 return -ENOMEM; in pci_register_io_range()
4184 range->fwnode = fwnode; in pci_register_io_range()
4185 range->size = size; in pci_register_io_range()
4186 range->hw_start = addr; in pci_register_io_range()
4187 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4194 if (ret == -EEXIST) in pci_register_io_range()
4218 return (unsigned long)-1; in pci_address_to_pio()
4225 * pci_remap_iospace - Remap the memory mapped I/O space
4238 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4240 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4241 return -EINVAL; in pci_remap_iospace()
4243 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4244 return -EINVAL; in pci_remap_iospace()
4254 return -ENODEV; in pci_remap_iospace()
4261 * pci_unmap_iospace - Unmap the memory mapped I/O space
4271 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4292 dev->is_busmaster = enable; in __pci_set_master()
4296 * pcibios_setup - process "pci=" kernel boot arguments
4308 * pcibios_set_master - enable PCI bus-mastering for device dev
4311 * Enables PCI bus-mastering for the device. This is the default
4335 * pci_set_master - enables bus-mastering for device dev
4338 * Enables bus-mastering on the device and calls pcibios_set_master()
4349 * pci_clear_master - disables bus-mastering for device dev
4359 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4364 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4366 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4373 return -EINVAL; in pci_set_cacheline_size()
4392 return -EINVAL; in pci_set_cacheline_size()
4397 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4400 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4402 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4418 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4428 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4431 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4434 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4447 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4450 * Disables PCI Memory-Write-Invalidate transaction on the device
4467 * pci_disable_parity - disable parity checking for device
4484 * pci_intx - enables/disables PCI INTx for device dev
4519 * pci_wait_for_pending_transaction - wait for pending transaction
4535 * pcie_flr - initiate a PCIe function level reset
4548 if (dev->imm_ready) in pcie_flr()
4553 * 100ms, but may silently discard requests while the FLR is in in pcie_flr()
4554 * progress. Wait 100ms before trying to access the device. in pcie_flr()
4563 * pcie_reset_flr - initiate a PCIe function level reset
4571 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4572 return -ENOTTY; in pcie_reset_flr()
4574 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4575 return -ENOTTY; in pcie_reset_flr()
4591 return -ENOTTY; in pci_af_flr()
4593 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4594 return -ENOTTY; in pci_af_flr()
4598 return -ENOTTY; in pci_af_flr()
4604 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4614 if (dev->imm_ready) in pci_af_flr()
4620 * 100ms, but may silently discard requests while the FLR is in in pci_af_flr()
4621 * progress. Wait 100ms before trying to access the device. in pci_af_flr()
4629 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4635 * PCI_D0. If that's the case and the device is not in a low-power state
4639 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4647 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4648 return -ENOTTY; in pci_pm_reset()
4650 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4652 return -ENOTTY; in pci_pm_reset()
4657 if (dev->current_state != PCI_D0) in pci_pm_reset()
4658 return -EINVAL; in pci_pm_reset()
4662 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4667 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4670 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4674 * pcie_wait_for_link_status - Wait for link status change
4679 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
4700 return -ETIMEDOUT; in pcie_wait_for_link_status()
4704 * pcie_retrain_link - Request a link retrain and wait for it to complete
4712 * Return 0 if successful, or -ETIMEDOUT if training has not completed
4731 if (pdev->clear_retrain_link) { in pcie_retrain_link()
4752 * pcie_wait_for_link_delay - Wait until link is active or inactive
4755 * @delay: Delay to wait after link has become active (in ms)
4766 * case, we wait for 1000 ms + any delay requested by the caller. in pcie_wait_for_link_delay()
4768 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
4774 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, in pcie_wait_for_link_delay()
4776 * successful. If so, software must wait a minimum 100ms before sending in pcie_wait_for_link_delay()
4802 * pcie_wait_for_link - Wait until link is active or inactive
4815 * spec says 100 ms, but firmware can lower it and we allow drivers to
4826 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
4827 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
4828 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4829 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
4830 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4837 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4839 * @reset_type: reset type in human-readable form
4849 * Return 0 on success or -ENOTTY if the first device on the secondary bus
4867 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
4871 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
4877 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
4883 child = pci_dev_get(list_first_entry(&dev->subordinate->devices, in pci_bridge_wait_for_secondary_bus()
4888 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
4889 * accessing the device after reset (that is 1000 ms + 100 ms). in pci_bridge_wait_for_secondary_bus()
4892 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay); in pci_bridge_wait_for_secondary_bus()
4899 * greater than 5 GT/s need to wait minimum 100 ms. For higher in pci_bridge_wait_for_secondary_bus()
4903 * However, 100 ms is the minimum and the PCIe spec says the in pci_bridge_wait_for_secondary_bus()
4909 * Therefore we wait for 100 ms and check for the device presence in pci_bridge_wait_for_secondary_bus()
4918 pci_dbg(dev, "waiting %d ms for downstream link\n", delay); in pci_bridge_wait_for_secondary_bus()
4921 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay)) in pci_bridge_wait_for_secondary_bus()
4929 if (!dev->link_active_reporting) in pci_bridge_wait_for_secondary_bus()
4930 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4934 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4937 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT); in pci_bridge_wait_for_secondary_bus()
4940 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", in pci_bridge_wait_for_secondary_bus()
4945 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4949 PCIE_RESET_READY_POLL_MS - delay); in pci_bridge_wait_for_secondary_bus()
4961 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double in pci_reset_secondary_bus()
4962 * this to 2ms to ensure that we meet the minimum requirement. in pci_reset_secondary_bus()
4976 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4979 * Use the bridge control register to assert reset on the secondary bus.
4980 * Devices on the secondary bus are left in power-on state.
4984 if (!dev->block_cfg_access) in pci_bridge_secondary_bus_reset()
4997 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
4998 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
4999 return -ENOTTY; in pci_parent_bus_reset()
5001 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
5003 return -ENOTTY; in pci_parent_bus_reset()
5008 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5013 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5015 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5018 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5019 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5021 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5028 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5029 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5030 return -ENOTTY; in pci_dev_reset_slot_function()
5032 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5078 return -ENOTTY; in pci_reset_bus_function()
5082 if (rc != -ENOTTY) in pci_reset_bus_function()
5095 return -ENOTTY; in cxl_reset_bus_function()
5099 return -ENOTTY; in cxl_reset_bus_function()
5106 return -ENOTTY; in cxl_reset_bus_function()
5128 device_lock(&dev->dev); in pci_dev_lock()
5136 if (device_trylock(&dev->dev)) { in pci_dev_trylock()
5139 device_unlock(&dev->dev); in pci_dev_trylock()
5149 device_unlock(&dev->dev); in pci_dev_unlock()
5156 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5159 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5160 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5163 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5164 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5167 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5169 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5176 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5178 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5179 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5187 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5192 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5193 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5196 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5197 err_handler->reset_done(dev); in pci_dev_restore()
5200 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5220 m = pdev->reset_methods[i]; in reset_method_show()
5256 pdev->reset_methods[0] = 0; in reset_method_store()
5268 return -ENOMEM; in reset_method_store()
5288 if (n == PCI_NUM_RESET_METHODS - 1) { in reset_method_store()
5298 /* Warn if dev-specific supported but not highest priority */ in reset_method_store()
5301 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user"); in reset_method_store()
5302 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods)); in reset_method_store()
5309 return -EINVAL; in reset_method_store()
5326 return a->mode; in pci_dev_reset_method_attr_is_visible()
5335 * __pci_reset_function_locked - reset a PCI device function while holding
5361 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5369 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5371 return -ENOTTY; in __pci_reset_function_locked()
5376 if (rc != -ENOTTY) in __pci_reset_function_locked()
5380 return -ENOTTY; in __pci_reset_function_locked()
5385 * pci_init_reset_methods - check whether device can be safely reset
5390 * other functions in the same device. The PCI device must be in D0-D3hot
5408 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5409 else if (rc != -ENOTTY) in pci_init_reset_methods()
5413 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5417 * pci_reset_function - quiesce and reset a PCI device function
5438 return -ENOTTY; in pci_reset_function()
5464 * pci_reset_function_locked - quiesce and reset a PCI device function
5485 return -ENOTTY; in pci_reset_function_locked()
5498 * pci_try_reset_function - quiesce and reset a PCI device function
5501 * Same as above, except return -EAGAIN if unable to lock device.
5508 return -ENOTTY; in pci_try_reset_function()
5511 return -EAGAIN; in pci_try_reset_function()
5528 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resettable()
5531 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resettable()
5532 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resettable()
5533 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_bus_resettable()
5545 pci_dev_lock(bus->self); in pci_bus_lock()
5546 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5547 if (dev->subordinate) in pci_bus_lock()
5548 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5559 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5560 if (dev->subordinate) in pci_bus_unlock()
5561 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5565 pci_dev_unlock(bus->self); in pci_bus_unlock()
5573 if (!pci_dev_trylock(bus->self)) in pci_bus_trylock()
5576 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5577 if (dev->subordinate) { in pci_bus_trylock()
5578 if (!pci_bus_trylock(dev->subordinate)) in pci_bus_trylock()
5586 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5587 if (dev->subordinate) in pci_bus_trylock()
5588 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5592 pci_dev_unlock(bus->self); in pci_bus_trylock()
5601 if (slot->bus->self && in pci_slot_resettable()
5602 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resettable()
5605 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resettable()
5606 if (!dev->slot || dev->slot != slot) in pci_slot_resettable()
5608 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resettable()
5609 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_slot_resettable()
5621 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5622 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5624 if (dev->subordinate) in pci_slot_lock()
5625 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5636 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5637 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5639 if (dev->subordinate) in pci_slot_unlock()
5640 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5650 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5651 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5653 if (dev->subordinate) { in pci_slot_trylock()
5654 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5665 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5666 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5668 if (dev->subordinate) in pci_slot_trylock()
5669 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5684 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5686 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5687 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5700 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5702 if (dev->subordinate) { in pci_bus_restore_locked()
5704 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5717 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5718 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5721 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5722 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5735 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5736 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5739 if (dev->subordinate) { in pci_slot_restore_locked()
5741 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5751 return -ENOTTY; in pci_slot_reset()
5758 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5767 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5779 * __pci_reset_slot - Try to reset a PCI slot
5791 * Same as above except return -EAGAIN if the slot cannot be locked
5804 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
5808 rc = -EAGAIN; in __pci_reset_slot()
5817 if (!bus->self || !pci_bus_resettable(bus)) in pci_bus_reset()
5818 return -ENOTTY; in pci_bus_reset()
5827 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
5835 * pci_bus_error_reset - reset the bridge's subordinate bus
5844 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
5848 return -ENOTTY; in pci_bus_error_reset()
5851 if (list_empty(&bus->slots)) in pci_bus_error_reset()
5854 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5858 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5866 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
5870 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5882 * __pci_reset_bus - Try to reset a PCI bus
5885 * Same as above except return -EAGAIN if the bus cannot be locked
5898 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
5902 rc = -EAGAIN; in __pci_reset_bus()
5908 * pci_reset_bus - Try to reset a PCI bus
5911 * Same as above except return -EAGAIN if the bus cannot be locked
5915 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
5916 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
5921 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5934 return -EINVAL; in pcix_get_max_mmrbc()
5937 return -EINVAL; in pcix_get_max_mmrbc()
5944 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5957 return -EINVAL; in pcix_get_mmrbc()
5960 return -EINVAL; in pcix_get_mmrbc()
5967 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5982 return -EINVAL; in pcix_set_mmrbc()
5984 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
5988 return -EINVAL; in pcix_set_mmrbc()
5991 return -EINVAL; in pcix_set_mmrbc()
5994 return -E2BIG; in pcix_set_mmrbc()
5997 return -EINVAL; in pcix_set_mmrbc()
6001 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
6002 return -EIO; in pcix_set_mmrbc()
6007 return -EIO; in pcix_set_mmrbc()
6014 * pcie_get_readrq - get PCI Express read request size
6030 * pcie_set_readrq - set PCI Express maximum memory read request
6041 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); in pcie_set_readrq()
6044 return -EINVAL; in pcie_set_readrq()
6058 v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8); in pcie_set_readrq()
6060 if (bridge->no_inc_mrrs) { in pcie_set_readrq()
6065 return -EINVAL; in pcie_set_readrq()
6077 * pcie_get_mps - get PCI Express maximum payload size
6093 * pcie_set_mps - set PCI Express maximum payload size
6106 return -EINVAL; in pcie_set_mps()
6108 v = ffs(mps) - 8; in pcie_set_mps()
6109 if (v > dev->pcie_mpss) in pcie_set_mps()
6110 return -EINVAL; in pcie_set_mps()
6139 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6196 * pcie_get_speed_cap - query for the PCI device's link speed capability
6217 /* PCIe r3.0-compliant */ in pcie_get_speed_cap()
6232 * pcie_get_width_cap - query for the PCI device's link width capability
6251 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6274 * __pcie_print_link_status - Report the PCI device's link speed and width
6307 * pcie_print_link_status - Report the PCI device's link speed and width
6319 * pci_select_bars - Make BAR mask from the type of resource
6353 * pci_set_vga_state - set VGA decode state on device and parents if requested
6387 bus = dev->bus; in pci_set_vga_state()
6389 bridge = bus->self; in pci_set_vga_state()
6400 bus = bus->parent; in pci_set_vga_state()
6413 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6417 return adev->power.flags.power_resources && in pci_pr3_present()
6418 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6424 * pci_add_dma_alias - Add a DMA devfn alias for a device
6429 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6430 * which is used to program permissible bus-devfn source addresses for DMA
6433 * from their logical bus-devfn. Examples include device quirks where the
6434 * device simply uses the wrong devfn, as well as non-transparent bridges
6448 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6449 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6451 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6452 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6453 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6458 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6471 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6472 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6473 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6474 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6487 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6493 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6495 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6498 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6503 * pci_real_dma_dev - Get PCI DMA device for PCI device
6506 * Permits the platform to provide architecture-specific functionality to
6523 * Arches that don't want to expose struct resource to userland as-is in
6530 *start = rsrc->start; in pci_resource_to_user()
6531 *end = rsrc->end; in pci_resource_to_user()
6538 * pci_specified_resource_alignment - get resource alignment specified by user.
6602 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6606 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6609 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6636 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6651 r->start = 0; in pci_request_resource_alignment()
6652 r->end = align - 1; in pci_request_resource_alignment()
6654 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6655 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6656 r->start = align; in pci_request_resource_alignment()
6657 r->end = r->start + size - 1; in pci_request_resource_alignment()
6659 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6666 * Later on, the kernel will assign page-aligned memory resource back
6678 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6680 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6683 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6691 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6692 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6709 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6711 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6712 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6714 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6715 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6716 r->start = 0; in pci_reassigndev_resource_alignment()
6739 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6740 return -EINVAL; in resource_alignment_store()
6744 return -ENOMEM; in resource_alignment_store()
6820 domain_nr = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
6842 if (of_get_pci_domain_nr(parent->of_node) == domain_nr) in of_pci_bus_release_domain_nr()
6863 * pci_ext_cfg_avail - can we access extended PCI config space?