318 pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value)  in pci_bridge_emul_read_ssid()  argument
323 			((bridge->pcie_start > bridge->ssid_start) ? (bridge->pcie_start << 8) : 0);  in pci_bridge_emul_read_ssid()
327 		*value = bridge->subsystem_vendor_id |  in pci_bridge_emul_read_ssid()
328 			(bridge->subsystem_id << 16);  in pci_bridge_emul_read_ssid()
343 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,  in pci_bridge_emul_init()  argument
346 	BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);  in pci_bridge_emul_init()
353 	bridge->conf.class_revision |=  in pci_bridge_emul_init()
355 	bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;  in pci_bridge_emul_init()
356 	bridge->conf.cache_line_size = 0x10;  in pci_bridge_emul_init()
357 	bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);  in pci_bridge_emul_init()
358 	bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,  in pci_bridge_emul_init()
361 	if (!bridge->pci_regs_behavior)  in pci_bridge_emul_init()
365 	if (!bridge->ssid_start && !bridge->pcie_start) {  in pci_bridge_emul_init()
366 		if (bridge->subsystem_vendor_id)  in pci_bridge_emul_init()
367 			bridge->ssid_start = PCI_BRIDGE_CONF_END;  in pci_bridge_emul_init()
368 		if (bridge->has_pcie)  in pci_bridge_emul_init()
369 			bridge->pcie_start = bridge->ssid_start + PCI_CAP_SSID_SIZEOF;  in pci_bridge_emul_init()
370 	} else if (!bridge->ssid_start && bridge->subsystem_vendor_id) {  in pci_bridge_emul_init()
371 		if (bridge->pcie_start - PCI_BRIDGE_CONF_END >= PCI_CAP_SSID_SIZEOF)  in pci_bridge_emul_init()
372 			bridge->ssid_start = PCI_BRIDGE_CONF_END;  in pci_bridge_emul_init()
374 			bridge->ssid_start = bridge->pcie_start + PCI_CAP_PCIE_SIZEOF;  in pci_bridge_emul_init()
375 	} else if (!bridge->pcie_start && bridge->has_pcie) {  in pci_bridge_emul_init()
376 		if (bridge->ssid_start - PCI_BRIDGE_CONF_END >= PCI_CAP_PCIE_SIZEOF)  in pci_bridge_emul_init()
377 			bridge->pcie_start = PCI_BRIDGE_CONF_END;  in pci_bridge_emul_init()
379 			bridge->pcie_start = bridge->ssid_start + PCI_CAP_SSID_SIZEOF;  in pci_bridge_emul_init()
382 	bridge->conf.capabilities_pointer = min(bridge->ssid_start, bridge->pcie_start);  in pci_bridge_emul_init()
384 	if (bridge->conf.capabilities_pointer)  in pci_bridge_emul_init()
385 		bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);  in pci_bridge_emul_init()
387 	if (bridge->has_pcie) {  in pci_bridge_emul_init()
388 		bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;  in pci_bridge_emul_init()
389 		bridge->pcie_conf.next = (bridge->ssid_start > bridge->pcie_start) ?  in pci_bridge_emul_init()
390 					 bridge->ssid_start : 0;  in pci_bridge_emul_init()
391 		bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);  in pci_bridge_emul_init()
392 		bridge->pcie_cap_regs_behavior =  in pci_bridge_emul_init()
396 		if (!bridge->pcie_cap_regs_behavior) {  in pci_bridge_emul_init()
397 			kfree(bridge->pci_regs_behavior);  in pci_bridge_emul_init()
401 		bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=  in pci_bridge_emul_init()
403 		bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=  in pci_bridge_emul_init()
409 		bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=  in pci_bridge_emul_init()
411 		bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=  in pci_bridge_emul_init()
414 		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=  in pci_bridge_emul_init()
417 		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=  in pci_bridge_emul_init()
419 		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=  in pci_bridge_emul_init()
424 		bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;  in pci_bridge_emul_init()
425 		bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;  in pci_bridge_emul_init()
429 		bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;  in pci_bridge_emul_init()
430 		bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;  in pci_bridge_emul_init()
431 		bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);  in pci_bridge_emul_init()
432 		bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);  in pci_bridge_emul_init()
433 		bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0;  in pci_bridge_emul_init()
434 		bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;  in pci_bridge_emul_init()
445 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)  in pci_bridge_emul_cleanup()  argument
447 	if (bridge->has_pcie)  in pci_bridge_emul_cleanup()
448 		kfree(bridge->pcie_cap_regs_behavior);  in pci_bridge_emul_cleanup()
449 	kfree(bridge->pci_regs_behavior);  in pci_bridge_emul_cleanup()
458 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,  in pci_bridge_emul_conf_read()  argument
463 	pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,  in pci_bridge_emul_conf_read()
470 		read_op = bridge->ops->read_base;  in pci_bridge_emul_conf_read()
471 		cfgspace = (__le32 *) &bridge->conf;  in pci_bridge_emul_conf_read()
472 		behavior = bridge->pci_regs_behavior;  in pci_bridge_emul_conf_read()
473 	} else if (reg >= bridge->ssid_start && reg < bridge->ssid_start + PCI_CAP_SSID_SIZEOF &&  in pci_bridge_emul_conf_read()
474 		   bridge->subsystem_vendor_id) {  in pci_bridge_emul_conf_read()
476 		reg -= bridge->ssid_start;  in pci_bridge_emul_conf_read()
480 	} else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&  in pci_bridge_emul_conf_read()
481 		   bridge->has_pcie) {  in pci_bridge_emul_conf_read()
483 		reg -= bridge->pcie_start;  in pci_bridge_emul_conf_read()
484 		read_op = bridge->ops->read_pcie;  in pci_bridge_emul_conf_read()
485 		cfgspace = (__le32 *) &bridge->pcie_conf;  in pci_bridge_emul_conf_read()
486 		behavior = bridge->pcie_cap_regs_behavior;  in pci_bridge_emul_conf_read()
487 	} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {  in pci_bridge_emul_conf_read()
490 		read_op = bridge->ops->read_ext;  in pci_bridge_emul_conf_read()
500 		ret = read_op(bridge, reg, value);  in pci_bridge_emul_conf_read()
535 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,  in pci_bridge_emul_conf_write()  argument
540 	void (*write_op)(struct pci_bridge_emul *bridge, int reg,  in pci_bridge_emul_conf_write()
545 	ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);  in pci_bridge_emul_conf_write()
551 		write_op = bridge->ops->write_base;  in pci_bridge_emul_conf_write()
552 		cfgspace = (__le32 *) &bridge->conf;  in pci_bridge_emul_conf_write()
553 		behavior = bridge->pci_regs_behavior;  in pci_bridge_emul_conf_write()
554 	} else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&  in pci_bridge_emul_conf_write()
555 		   bridge->has_pcie) {  in pci_bridge_emul_conf_write()
557 		reg -= bridge->pcie_start;  in pci_bridge_emul_conf_write()
558 		write_op = bridge->ops->write_pcie;  in pci_bridge_emul_conf_write()
559 		cfgspace = (__le32 *) &bridge->pcie_conf;  in pci_bridge_emul_conf_write()
560 		behavior = bridge->pcie_cap_regs_behavior;  in pci_bridge_emul_conf_write()
561 	} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {  in pci_bridge_emul_conf_write()
564 		write_op = bridge->ops->write_ext;  in pci_bridge_emul_conf_write()
617 		write_op(bridge, reg, old, new, mask);  in pci_bridge_emul_conf_write()