169 static void start_int_poll_timer(struct controller *ctrl, int sec);
171 static inline u8 shpc_readb(struct controller *ctrl, int reg)  in shpc_readb()  argument
173 	return readb(ctrl->creg + reg);  in shpc_readb()
176 static inline u16 shpc_readw(struct controller *ctrl, int reg)  in shpc_readw()  argument
178 	return readw(ctrl->creg + reg);  in shpc_readw()
181 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)  in shpc_writew()  argument
183 	writew(val, ctrl->creg + reg);  in shpc_writew()
186 static inline u32 shpc_readl(struct controller *ctrl, int reg)  in shpc_readl()  argument
188 	return readl(ctrl->creg + reg);  in shpc_readl()
191 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)  in shpc_writel()  argument
193 	writel(val, ctrl->creg + reg);  in shpc_writel()
196 static inline int shpc_indirect_read(struct controller *ctrl, int index,  in shpc_indirect_read()  argument
200 	u32 cap_offset = ctrl->cap_offset;  in shpc_indirect_read()
201 	struct pci_dev *pdev = ctrl->pci_dev;  in shpc_indirect_read()
214 	struct controller *ctrl = from_timer(ctrl, t, poll_timer);  in int_poll_timeout()  local
217 	shpc_isr(0, ctrl);  in int_poll_timeout()
222 	start_int_poll_timer(ctrl, shpchp_poll_time);  in int_poll_timeout()
228 static void start_int_poll_timer(struct controller *ctrl, int sec)  in start_int_poll_timer()  argument
234 	ctrl->poll_timer.expires = jiffies + sec * HZ;  in start_int_poll_timer()
235 	add_timer(&ctrl->poll_timer);  in start_int_poll_timer()
238 static inline int is_ctrl_busy(struct controller *ctrl)  in is_ctrl_busy()  argument
240 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);  in is_ctrl_busy()
248 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)  in shpc_poll_ctrl_busy()  argument
252 	if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
258 		if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
265 static inline int shpc_wait_cmd(struct controller *ctrl)  in shpc_wait_cmd()  argument
272 		rc = shpc_poll_ctrl_busy(ctrl);  in shpc_wait_cmd()
274 		rc = wait_event_interruptible_timeout(ctrl->queue,  in shpc_wait_cmd()
275 						!is_ctrl_busy(ctrl), timeout);  in shpc_wait_cmd()
276 	if (!rc && is_ctrl_busy(ctrl)) {  in shpc_wait_cmd()
278 		ctrl_err(ctrl, "Command not completed in 1000 msec\n");  in shpc_wait_cmd()
281 		ctrl_info(ctrl, "Command was interrupted by a signal\n");  in shpc_wait_cmd()
289 	struct controller *ctrl = slot->ctrl;  in shpc_write_cmd()  local
294 	mutex_lock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
296 	if (!shpc_poll_ctrl_busy(ctrl)) {  in shpc_write_cmd()
298 		ctrl_err(ctrl, "Controller is still busy after 1 sec\n");  in shpc_write_cmd()
305 	ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);  in shpc_write_cmd()
310 	shpc_writew(ctrl, CMD, temp_word);  in shpc_write_cmd()
315 	retval = shpc_wait_cmd(slot->ctrl);  in shpc_write_cmd()
319 	cmd_status = shpchp_check_cmd_status(slot->ctrl);  in shpc_write_cmd()
321 		ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",  in shpc_write_cmd()
326 	mutex_unlock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
330 int shpchp_check_cmd_status(struct controller *ctrl)  in shpchp_check_cmd_status()  argument
333 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;  in shpchp_check_cmd_status()
341 		ctrl_err(ctrl, "Switch opened!\n");  in shpchp_check_cmd_status()
345 		ctrl_err(ctrl, "Invalid HPC command!\n");  in shpchp_check_cmd_status()
349 		ctrl_err(ctrl, "Invalid bus speed/mode!\n");  in shpchp_check_cmd_status()
361 	struct controller *ctrl = slot->ctrl;  in shpchp_get_attention_status()  local
362 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in shpchp_get_attention_status()
385 	struct controller *ctrl = slot->ctrl;  in shpchp_get_power_status()  local
386 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in shpchp_get_power_status()
410 	struct controller *ctrl = slot->ctrl;  in shpchp_get_latch_status()  local
411 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in shpchp_get_latch_status()
420 	struct controller *ctrl = slot->ctrl;  in shpchp_get_adapter_status()  local
421 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in shpchp_get_adapter_status()
431 	struct controller *ctrl = slot->ctrl;  in shpchp_get_prog_int()  local
433 	*prog_int = shpc_readb(ctrl, PROG_INTERFACE);  in shpchp_get_prog_int()
441 	struct controller *ctrl = slot->ctrl;  in shpchp_get_adapter_speed()  local
442 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in shpchp_get_adapter_speed()
461 	ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",  in shpchp_get_adapter_speed()
487 	ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);  in shpchp_get_adapter_speed()
493 	struct controller *ctrl = slot->ctrl;  in shpchp_query_power_fault()  local
494 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in shpchp_query_power_fault()
537 void shpchp_release_ctlr(struct controller *ctrl)  in shpchp_release_ctlr()  argument
545 	for (i = 0; i < ctrl->num_slots; i++) {  in shpchp_release_ctlr()
546 		slot_reg = shpc_readl(ctrl, SLOT_REG(i));  in shpchp_release_ctlr()
552 		shpc_writel(ctrl, SLOT_REG(i), slot_reg);  in shpchp_release_ctlr()
555 	cleanup_slots(ctrl);  in shpchp_release_ctlr()
560 	serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpchp_release_ctlr()
564 	shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpchp_release_ctlr()
567 		del_timer(&ctrl->poll_timer);  in shpchp_release_ctlr()
569 		free_irq(ctrl->pci_dev->irq, ctrl);  in shpchp_release_ctlr()
570 		pci_disable_msi(ctrl->pci_dev);  in shpchp_release_ctlr()
573 	iounmap(ctrl->creg);  in shpchp_release_ctlr()
574 	release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in shpchp_release_ctlr()
583 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in shpchp_power_on_slot()
596 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in shpchp_slot_enable()
609 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in shpchp_slot_disable()
614 static int shpc_get_cur_bus_speed(struct controller *ctrl)  in shpc_get_cur_bus_speed()  argument
617 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_cur_bus_speed()
619 	u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);  in shpc_get_cur_bus_speed()
620 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_cur_bus_speed()
686 	struct controller *ctrl = slot->ctrl;  in shpchp_set_bus_speed_mode()  local
689 	pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpchp_set_bus_speed_mode()
742 		ctrl_err(ctrl, "%s: Write command failed!\n", __func__);  in shpchp_set_bus_speed_mode()
744 		shpc_get_cur_bus_speed(ctrl);  in shpchp_set_bus_speed_mode()
751 	struct controller *ctrl = (struct controller *)dev_id;  in shpc_isr()  local
756 	intr_loc = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
760 	ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);  in shpc_isr()
767 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
770 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
772 		intr_loc2 = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
773 		ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);  in shpc_isr()
782 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
784 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
786 		wake_up_interruptible(&ctrl->queue);  in shpc_isr()
792 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_isr()
797 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_isr()
798 		ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",  in shpc_isr()
802 			shpchp_handle_switch_change(hp_slot, ctrl);  in shpc_isr()
805 			shpchp_handle_attention_button(hp_slot, ctrl);  in shpc_isr()
808 			shpchp_handle_presence_change(hp_slot, ctrl);  in shpc_isr()
811 			shpchp_handle_power_fault(hp_slot, ctrl);  in shpc_isr()
815 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_isr()
820 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
822 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
828 static int shpc_get_max_bus_speed(struct controller *ctrl)  in shpc_get_max_bus_speed()  argument
831 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_max_bus_speed()
833 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_max_bus_speed()
834 	u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);  in shpc_get_max_bus_speed()
835 	u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);  in shpc_get_max_bus_speed()
868 	ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);  in shpc_get_max_bus_speed()
873 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)  in shpc_init()  argument
881 	ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */  in shpc_init()
882 	ctrl_dbg(ctrl, "Hotplug Controller:\n");  in shpc_init()
887 		ctrl->mmio_base = pci_resource_start(pdev, 0);  in shpc_init()
888 		ctrl->mmio_size = pci_resource_len(pdev, 0);  in shpc_init()
890 		ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);  in shpc_init()
891 		if (!ctrl->cap_offset) {  in shpc_init()
892 			ctrl_err(ctrl, "Cannot find PCI capability\n");  in shpc_init()
895 		ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);  in shpc_init()
897 		rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);  in shpc_init()
899 			ctrl_err(ctrl, "Cannot read base_offset\n");  in shpc_init()
903 		rc = shpc_indirect_read(ctrl, 3, &tempdword);  in shpc_init()
905 			ctrl_err(ctrl, "Cannot read slot config\n");  in shpc_init()
909 		ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);  in shpc_init()
912 			rc = shpc_indirect_read(ctrl, i, &tempdword);  in shpc_init()
914 				ctrl_err(ctrl, "Cannot read creg (index = %d)\n",  in shpc_init()
918 			ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);  in shpc_init()
921 		ctrl->mmio_base =  in shpc_init()
923 		ctrl->mmio_size = 0x24 + 0x4 * num_slots;  in shpc_init()
926 	ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",  in shpc_init()
932 		ctrl_err(ctrl, "pci_enable_device failed\n");  in shpc_init()
936 	if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {  in shpc_init()
937 		ctrl_err(ctrl, "Cannot reserve MMIO region\n");  in shpc_init()
942 	ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
943 	if (!ctrl->creg) {  in shpc_init()
944 		ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",  in shpc_init()
945 			 ctrl->mmio_size, ctrl->mmio_base);  in shpc_init()
946 		release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
950 	ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);  in shpc_init()
952 	mutex_init(&ctrl->crit_sect);  in shpc_init()
953 	mutex_init(&ctrl->cmd_lock);  in shpc_init()
956 	init_waitqueue_head(&ctrl->queue);  in shpc_init()
959 	slot_config = shpc_readl(ctrl, SLOT_CONFIG);  in shpc_init()
960 	ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;  in shpc_init()
961 	ctrl->num_slots = slot_config & SLOT_NUM;  in shpc_init()
962 	ctrl->first_slot = (slot_config & PSN) >> 16;  in shpc_init()
963 	ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;  in shpc_init()
966 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
967 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
971 	shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
972 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
973 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
978 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
979 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
980 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
987 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
992 		timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);  in shpc_init()
993 		start_int_poll_timer(ctrl, 10);  in shpc_init()
998 			ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");  in shpc_init()
999 			ctrl_info(ctrl, "Use INTx for the hotplug controller\n");  in shpc_init()
1004 		rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,  in shpc_init()
1005 				 MY_NAME, (void *)ctrl);  in shpc_init()
1006 		ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",  in shpc_init()
1007 			 ctrl->pci_dev->irq, rc);  in shpc_init()
1009 			ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",  in shpc_init()
1010 				 ctrl->pci_dev->irq);  in shpc_init()
1014 	ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);  in shpc_init()
1016 	shpc_get_max_bus_speed(ctrl);  in shpc_init()
1017 	shpc_get_cur_bus_speed(ctrl);  in shpc_init()
1022 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
1023 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
1024 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
1029 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
1033 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1036 		shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
1037 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1038 		ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1045 	iounmap(ctrl->creg);  in shpc_init()