pci/controller/pcie-mt7621.c

12  * support RT2880/RT3883 PCIe
15  * support RT6855/MT7620 PCIe
48 /* PCIe RC control registers */
67  * struct mt7621_pcie_port - PCIe port information
70  * @pcie: pointer to PCIe host info
81 	struct mt7621_pcie *pcie;  member
91  * struct mt7621_pcie - PCIe host information
93  * @dev: Pointer to PCIe device
94  * @ports: pointer to PCIe port information
105 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)  in pcie_read()  argument
107 	return readl_relaxed(pcie->base + reg);  in pcie_read()
110 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)  in pcie_write()  argument
112 	writel_relaxed(val, pcie->base + reg);  in pcie_write()
129 	struct mt7621_pcie *pcie = bus->sysdata;  in mt7621_pcie_map_bus()  local
133 	writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);  in mt7621_pcie_map_bus()
135 	return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);  in mt7621_pcie_map_bus()
144 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)  in read_config()  argument
148 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);  in read_config()
149 	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);  in read_config()
152 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,  in write_config()  argument
157 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);  in write_config()
158 	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);  in write_config()
180 	struct mt7621_pcie *pcie = port->pcie;  in mt7621_control_assert()  local
182 	if (pcie->resets_inverted)  in mt7621_control_assert()
190 	struct mt7621_pcie *pcie = port->pcie;  in mt7621_control_deassert()  local
192 	if (pcie->resets_inverted)  in mt7621_control_deassert()
198 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,  in mt7621_pcie_parse_port()  argument
203 	struct device *dev = pcie->dev;  in mt7621_pcie_parse_port()
218 		dev_err(dev, "failed to get pcie%d clock\n", slot);  in mt7621_pcie_parse_port()
224 		dev_err(dev, "failed to get pcie%d reset control\n", slot);  in mt7621_pcie_parse_port()
228 	snprintf(name, sizeof(name), "pcie-phy%d", slot);  in mt7621_pcie_parse_port()
231 		dev_err(dev, "failed to get pcie-phy%d\n", slot);  in mt7621_pcie_parse_port()
239 		dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);  in mt7621_pcie_parse_port()
245 	port->pcie = pcie;  in mt7621_pcie_parse_port()
248 	list_add_tail(&port->list, &pcie->ports);  in mt7621_pcie_parse_port()
257 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)  in mt7621_pcie_parse_dt()  argument
259 	struct device *dev = pcie->dev;  in mt7621_pcie_parse_dt()
264 	pcie->base = devm_platform_ioremap_resource(pdev, 0);  in mt7621_pcie_parse_dt()
265 	if (IS_ERR(pcie->base))  in mt7621_pcie_parse_dt()
266 		return PTR_ERR(pcie->base);  in mt7621_pcie_parse_dt()
280 		err = mt7621_pcie_parse_port(pcie, child, slot);  in mt7621_pcie_parse_dt()
292 	struct mt7621_pcie *pcie = port->pcie;  in mt7621_pcie_init_port()  local
293 	struct device *dev = pcie->dev;  in mt7621_pcie_init_port()
315 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)  in mt7621_pcie_reset_assert()  argument
319 	list_for_each_entry(port, &pcie->ports, list) {  in mt7621_pcie_reset_assert()
320 		/* PCIe RC reset assert */  in mt7621_pcie_reset_assert()
323 		/* PCIe EP reset assert */  in mt7621_pcie_reset_assert()
330 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)  in mt7621_pcie_reset_rc_deassert()  argument
334 	list_for_each_entry(port, &pcie->ports, list)  in mt7621_pcie_reset_rc_deassert()
338 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)  in mt7621_pcie_reset_ep_deassert()  argument
342 	list_for_each_entry(port, &pcie->ports, list)  in mt7621_pcie_reset_ep_deassert()
348 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)  in mt7621_pcie_init_ports()  argument
350 	struct device *dev = pcie->dev;  in mt7621_pcie_init_ports()
355 	mt7621_pcie_reset_assert(pcie);  in mt7621_pcie_init_ports()
356 	mt7621_pcie_reset_rc_deassert(pcie);  in mt7621_pcie_init_ports()
358 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {  in mt7621_pcie_init_ports()
374 	mt7621_pcie_reset_ep_deassert(pcie);  in mt7621_pcie_init_ports()
377 	list_for_each_entry(port, &pcie->ports, list) {  in mt7621_pcie_init_ports()
381 			dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n",  in mt7621_pcie_init_ports()
402 	struct mt7621_pcie *pcie = port->pcie;  in mt7621_pcie_enable_port()  local
406 	/* enable pcie interrupt */  in mt7621_pcie_enable_port()
407 	val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);  in mt7621_pcie_enable_port()
409 	pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);  in mt7621_pcie_enable_port()
420 	val = read_config(pcie, slot, PCIE_FTS_NUM);  in mt7621_pcie_enable_port()
423 	write_config(pcie, slot, PCIE_FTS_NUM, val);  in mt7621_pcie_enable_port()
428 	struct mt7621_pcie *pcie = pci_host_bridge_priv(host);  in mt7621_pcie_enable_ports()  local
429 	struct device *dev = pcie->dev;  in mt7621_pcie_enable_ports()
441 	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);  in mt7621_pcie_enable_ports()
442 	pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);  in mt7621_pcie_enable_ports()
444 	list_for_each_entry(port, &pcie->ports, list) {  in mt7621_pcie_enable_ports()
448 				dev_err(dev, "enabling clk pcie%d\n",  in mt7621_pcie_enable_ports()
454 			dev_info(dev, "PCIE%d enabled\n", port->slot);  in mt7621_pcie_enable_ports()
463 	struct mt7621_pcie *pcie = pci_host_bridge_priv(host);  in mt7621_pcie_register_host()  local
466 	host->sysdata = pcie;  in mt7621_pcie_register_host()
480 	struct mt7621_pcie *pcie;  in mt7621_pcie_probe()  local
487 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in mt7621_pcie_probe()
491 	pcie = pci_host_bridge_priv(bridge);  in mt7621_pcie_probe()
492 	pcie->dev = dev;  in mt7621_pcie_probe()
493 	platform_set_drvdata(pdev, pcie);  in mt7621_pcie_probe()
494 	INIT_LIST_HEAD(&pcie->ports);  in mt7621_pcie_probe()
498 		pcie->resets_inverted = true;  in mt7621_pcie_probe()
500 	err = mt7621_pcie_parse_dt(pcie);  in mt7621_pcie_probe()
506 	err = mt7621_pcie_init_ports(pcie);  in mt7621_pcie_probe()
514 		dev_err(dev, "error enabling pcie ports\n");  in mt7621_pcie_probe()
521 	list_for_each_entry(port, &pcie->ports, list)  in mt7621_pcie_probe()
529 	struct mt7621_pcie *pcie = platform_get_drvdata(pdev);  in mt7621_pcie_remove()  local
532 	list_for_each_entry(port, &pcie->ports, list)  in mt7621_pcie_remove()
552 MODULE_DESCRIPTION("MediaTek MT7621 PCIe host controller driver");