Lines Matching full:pcie
40 /* Broadcom STB PCIe Register Offsets */
160 /* PCIe parameters */
194 #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) argument
195 #define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) argument
196 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) argument
197 #define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) argument
198 #define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE]) argument
242 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
243 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
269 /* Internal PCIe Host Controller Information.*/
288 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
289 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
296 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
298 return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425; in is_bmips()
367 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
373 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
378 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
385 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
391 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
403 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
405 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
406 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
409 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
412 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
415 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
425 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
426 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
432 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
437 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
439 if (is_bmips(pcie)) in brcm_pcie_set_outbound_win()
447 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
450 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
453 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
456 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
460 .name = "BRCM STB PCIe MSI",
602 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
604 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
633 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
637 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
651 msi->base = pcie->base; in brcm_pcie_enable_msi()
652 msi->np = pcie->np; in brcm_pcie_enable_msi()
653 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
655 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
664 msi->intr_base = msi->base + INTR2_CPU_BASE(pcie); in brcm_pcie_enable_msi()
680 pcie->msi = msi; in brcm_pcie_enable_msi()
686 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
688 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
694 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
696 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
706 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus() local
707 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
715 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_map_bus()
720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
727 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus() local
728 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
736 if (!brcm_pcie_link_up(pcie)) in brcm7425_pcie_map_bus()
741 writel(idx, base + IDX_ADDR(pcie)); in brcm7425_pcie_map_bus()
742 return base + DATA_ADDR(pcie); in brcm7425_pcie_map_bus()
745 static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
751 if (pcie->bridge_reset) { in brcm_pcie_bridge_sw_init_set_generic()
753 ret = reset_control_assert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
755 ret = reset_control_deassert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
758 dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n", in brcm_pcie_bridge_sw_init_set_generic()
764 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
766 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
771 static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
776 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
778 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
783 static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
787 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
791 ret = reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
793 ret = reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
796 dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n", in brcm_pcie_perst_set_4908()
801 static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
806 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
808 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
813 static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
817 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
819 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
833 static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, in brcm_pcie_get_inbound_wins() argument
836 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_inbound_wins()
839 struct device *dev = pcie->dev; in brcm_pcie_get_inbound_wins()
845 * The HW registers (and PCIe) use order-1 numbering for BARs. As such, in brcm_pcie_get_inbound_wins()
858 if (pcie->soc_base != BCM7712) in brcm_pcie_get_inbound_wins()
875 if (pcie->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
878 if (n > pcie->num_inbound_wins) in brcm_pcie_get_inbound_wins()
892 if (pcie->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
895 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_inbound_wins()
899 pcie->num_memc = 1; in brcm_pcie_get_inbound_wins()
900 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
902 pcie->num_memc = ret; in brcm_pcie_get_inbound_wins()
906 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
907 size += pcie->memc_size[i]; in brcm_pcie_get_inbound_wins()
924 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_inbound_wins()
929 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_inbound_wins()
932 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_inbound_wins()
943 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_inbound_wins()
987 static void set_inbound_win_registers(struct brcm_pcie *pcie, in set_inbound_win_registers() argument
991 void __iomem *base = pcie->base; in set_inbound_win_registers()
1015 if (pcie->soc_base == BCM7712) { in set_inbound_win_registers()
1027 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
1030 void __iomem *base = pcie->base; in brcm_pcie_setup()
1039 ret = pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
1044 if (pcie->soc_base == BCM2711) { in brcm_pcie_setup()
1045 ret = pcie->perst_set(pcie, 1); in brcm_pcie_setup()
1047 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1055 ret = pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1059 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_setup()
1060 if (is_bmips(pcie)) in brcm_pcie_setup()
1064 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_setup()
1073 if (is_bmips(pcie)) in brcm_pcie_setup()
1075 else if (pcie->soc_base == BCM2711) in brcm_pcie_setup()
1077 else if (pcie->soc_base == BCM7278) in brcm_pcie_setup()
1094 num_inbound_wins = brcm_pcie_get_inbound_wins(pcie, inbound_wins); in brcm_pcie_setup()
1098 set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins); in brcm_pcie_setup()
1100 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
1101 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
1106 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1107 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
1127 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
1129 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
1134 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1143 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1150 bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
1158 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1162 if (is_bmips(pcie)) { in brcm_pcie_setup()
1166 /* bmips PCIe outbound windows have a 128MB max size */ in brcm_pcie_setup()
1170 brcm_pcie_set_outbound_win(pcie, j, start, in brcm_pcie_setup()
1175 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1181 /* PCIe->SCB endian mode for inbound window */ in brcm_pcie_setup()
1193 * presence of a PCIe access.
1195 static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) in brcm_extend_rbus_timeout() argument
1198 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout()
1202 if (pcie->soc_base == BCM7712) in brcm_extend_rbus_timeout()
1206 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()
1209 static void brcm_config_clkreq(struct brcm_pcie *pcie) in brcm_config_clkreq() argument
1216 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); in brcm_config_clkreq()
1218 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1223 clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1231 * L1SS capable AND the OS enables L1SS, all PCIe traffic in brcm_config_clkreq()
1241 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1243 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1251 * section 3.2.5.2.2 of the PCIe spec. This situation is in brcm_config_clkreq()
1255 brcm_extend_rbus_timeout(pcie); in brcm_config_clkreq()
1263 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1266 writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1268 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); in brcm_config_clkreq()
1271 static int brcm_pcie_start_link(struct brcm_pcie *pcie) in brcm_pcie_start_link() argument
1273 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1274 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1280 ret = pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1285 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification in brcm_pcie_start_link()
1286 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1295 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1298 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_start_link()
1303 brcm_config_clkreq(pcie); in brcm_pcie_start_link()
1305 if (pcie->gen) in brcm_pcie_start_link()
1306 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1308 if (pcie->ssc) { in brcm_pcie_start_link()
1309 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_start_link()
1351 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus() local
1366 pcie->sr = sr; in brcm_pcie_add_bus()
1378 pcie->sr = NULL; in brcm_pcie_add_bus()
1383 brcm_pcie_start_link(pcie); in brcm_pcie_add_bus()
1389 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus() local
1390 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1399 pcie->sr = NULL; in brcm_pcie_remove_bus()
1402 /* L23 is a low-power PCIe link state */
1403 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1405 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1425 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1428 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1442 void __iomem *base = pcie->base; in brcm_phy_cntl()
1459 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1464 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1466 return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1469 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1471 return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1474 static int brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1476 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1479 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1480 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1482 ret = pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1492 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_turn_off()
1494 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_turn_off()
1496 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1497 ret = pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1515 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend_noirq() local
1516 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_suspend_noirq()
1519 ret = brcm_pcie_turn_off(pcie); in brcm_pcie_suspend_noirq()
1528 if (brcm_phy_stop(pcie)) in brcm_pcie_suspend_noirq()
1531 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1537 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1543 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1545 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1546 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1547 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1548 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1551 rret = reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1559 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1566 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume_noirq() local
1571 base = pcie->base; in brcm_pcie_resume_noirq()
1572 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1576 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1580 ret = brcm_phy_start(pcie); in brcm_pcie_resume_noirq()
1585 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1588 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_resume_noirq()
1590 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_resume_noirq()
1595 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume_noirq()
1599 if (pcie->sr) { in brcm_pcie_resume_noirq()
1600 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1607 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1609 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1610 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1618 ret = brcm_pcie_start_link(pcie); in brcm_pcie_resume_noirq()
1622 if (pcie->msi) in brcm_pcie_resume_noirq()
1623 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1628 if (pcie->sr) in brcm_pcie_resume_noirq()
1629 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1631 rret = reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1633 dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret); in brcm_pcie_resume_noirq()
1635 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1639 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1641 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1642 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1643 if (brcm_phy_stop(pcie)) in __brcm_pcie_remove()
1644 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1645 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1646 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1647 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1652 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1653 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1657 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1757 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1758 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1759 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1760 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
1761 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1762 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1763 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1764 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1765 { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
1790 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1793 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1803 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1804 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1805 pcie->np = np; in brcm_pcie_probe()
1806 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1807 pcie->soc_base = data->soc_base; in brcm_pcie_probe()
1808 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1809 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1810 pcie->has_phy = data->has_phy; in brcm_pcie_probe()
1811 pcie->num_inbound_wins = data->num_inbound_wins; in brcm_pcie_probe()
1813 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1814 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1815 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1817 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1818 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1819 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1822 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1824 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1826 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1827 if (IS_ERR(pcie->rescal)) in brcm_pcie_probe()
1828 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1830 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1831 if (IS_ERR(pcie->perst_reset)) in brcm_pcie_probe()
1832 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1834 pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); in brcm_pcie_probe()
1835 if (IS_ERR(pcie->bridge_reset)) in brcm_pcie_probe()
1836 return PTR_ERR(pcie->bridge_reset); in brcm_pcie_probe()
1838 pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); in brcm_pcie_probe()
1839 if (IS_ERR(pcie->swinit_reset)) in brcm_pcie_probe()
1840 return PTR_ERR(pcie->swinit_reset); in brcm_pcie_probe()
1842 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1846 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1848 if (pcie->swinit_reset) { in brcm_pcie_probe()
1849 ret = reset_control_assert(pcie->swinit_reset); in brcm_pcie_probe()
1851 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1859 ret = reset_control_deassert(pcie->swinit_reset); in brcm_pcie_probe()
1861 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1867 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1869 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1873 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1875 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1876 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1880 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1884 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1885 if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1886 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1891 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1892 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1893 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1895 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1900 bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1901 bridge->sysdata = pcie; in brcm_pcie_probe()
1903 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1906 if (!ret && !brcm_pcie_link_up(pcie)) in brcm_pcie_probe()
1917 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1933 .name = "brcm-pcie",
1941 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");