Lines Matching full:v3
3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
249 * The V3 PCI interface chip in Integrator provides several windows from
262 * There are three V3 windows, each described by a pair of V3 registers.
289 * The V3 chip translates an address by checking its range within
293 * LB_BASE1/LB_MAP1, the V3 will use the translation from
313 struct v3_pci *v3 = bus->sysdata; in v3_map_bus() local
365 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_map_bus()
367 v3->base + V3_LB_BASE0); in v3_map_bus()
373 writel(v3_addr_to_lb_base(v3->config_mem) | in v3_map_bus()
375 v3->base + V3_LB_BASE1); in v3_map_bus()
376 writew(mapaddress, v3->base + V3_LB_MAP1); in v3_map_bus()
378 return v3->config_base + address + offset; in v3_map_bus()
381 static void v3_unmap_bus(struct v3_pci *v3) in v3_unmap_bus() argument
386 writel(v3_addr_to_lb_base(v3->pre_mem) | in v3_unmap_bus()
389 v3->base + V3_LB_BASE1); in v3_unmap_bus()
390 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | in v3_unmap_bus()
392 v3->base + V3_LB_MAP1); in v3_unmap_bus()
397 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_unmap_bus()
399 v3->base + V3_LB_BASE0); in v3_unmap_bus()
405 struct v3_pci *v3 = bus->sysdata; in v3_pci_read_config() local
412 v3_unmap_bus(v3); in v3_pci_read_config()
419 struct v3_pci *v3 = bus->sysdata; in v3_pci_write_config() local
426 v3_unmap_bus(v3); in v3_pci_write_config()
438 struct v3_pci *v3 = data; in v3_irq() local
439 struct device *dev = v3->dev; in v3_irq()
442 status = readw(v3->base + V3_PCI_STAT); in v3_irq()
451 writew(status, v3->base + V3_PCI_STAT); in v3_irq()
453 status = readb(v3->base + V3_LB_ISTAT); in v3_irq()
471 writeb(0, v3->base + V3_LB_ISTAT); in v3_irq()
472 if (v3->map) in v3_irq()
473 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, in v3_irq()
480 static int v3_integrator_init(struct v3_pci *v3) in v3_integrator_init() argument
484 v3->map = in v3_integrator_init()
486 if (IS_ERR(v3->map)) { in v3_integrator_init()
487 dev_err(v3->dev, "no syscon\n"); in v3_integrator_init()
491 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); in v3_integrator_init()
493 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, in v3_integrator_init()
502 writel(0x6200, v3->base + V3_LB_IO_BASE); in v3_integrator_init()
506 writeb(0xaa, v3->base + V3_MAIL_DATA); in v3_integrator_init()
507 writeb(0x55, v3->base + V3_MAIL_DATA + 4); in v3_integrator_init()
508 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && in v3_integrator_init()
509 readb(v3->base + V3_MAIL_DATA) != 0x55); in v3_integrator_init()
512 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n"); in v3_integrator_init()
517 static int v3_pci_setup_resource(struct v3_pci *v3, in v3_pci_setup_resource() argument
521 struct device *dev = v3->dev; in v3_pci_setup_resource()
532 v3->base + V3_LB_BASE2); in v3_pci_setup_resource()
534 v3->base + V3_LB_MAP2); in v3_pci_setup_resource()
539 mem->name = "V3 PCI PRE-MEM"; in v3_pci_setup_resource()
540 v3->pre_mem = mem->start; in v3_pci_setup_resource()
541 v3->pre_bus_addr = mem->start - win->offset; in v3_pci_setup_resource()
543 mem, &v3->pre_bus_addr); in v3_pci_setup_resource()
548 if (v3->non_pre_mem && in v3_pci_setup_resource()
549 (mem->start != v3->non_pre_mem + SZ_256M)) { in v3_pci_setup_resource()
555 writel(v3_addr_to_lb_base(v3->pre_mem) | in v3_pci_setup_resource()
559 v3->base + V3_LB_BASE1); in v3_pci_setup_resource()
560 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | in v3_pci_setup_resource()
562 v3->base + V3_LB_MAP1); in v3_pci_setup_resource()
564 mem->name = "V3 PCI NON-PRE-MEM"; in v3_pci_setup_resource()
565 v3->non_pre_mem = mem->start; in v3_pci_setup_resource()
566 v3->non_pre_bus_addr = mem->start - win->offset; in v3_pci_setup_resource()
568 mem, &v3->non_pre_bus_addr); in v3_pci_setup_resource()
575 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_pci_setup_resource()
578 v3->base + V3_LB_BASE0); in v3_pci_setup_resource()
579 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) | in v3_pci_setup_resource()
581 v3->base + V3_LB_MAP0); in v3_pci_setup_resource()
595 static int v3_get_dma_range_config(struct v3_pci *v3, in v3_get_dma_range_config() argument
599 struct device *dev = v3->dev; in v3_get_dma_range_config()
657 dev_err(v3->dev, "illegal dma memory chunk size\n"); in v3_get_dma_range_config()
673 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3, in v3_pci_parse_map_dma_ranges() argument
676 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3); in v3_pci_parse_map_dma_ranges()
677 struct device *dev = v3->dev; in v3_pci_parse_map_dma_ranges()
685 ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map); in v3_pci_parse_map_dma_ranges()
690 writel(pci_base, v3->base + V3_PCI_BASE0); in v3_pci_parse_map_dma_ranges()
691 writel(pci_map, v3->base + V3_PCI_MAP0); in v3_pci_parse_map_dma_ranges()
693 writel(pci_base, v3->base + V3_PCI_BASE1); in v3_pci_parse_map_dma_ranges()
694 writel(pci_map, v3->base + V3_PCI_MAP1); in v3_pci_parse_map_dma_ranges()
710 struct v3_pci *v3; in v3_pci_probe() local
717 host = devm_pci_alloc_host_bridge(dev, sizeof(*v3)); in v3_pci_probe()
722 v3 = pci_host_bridge_priv(host); in v3_pci_probe()
723 host->sysdata = v3; in v3_pci_probe()
724 v3->dev = dev; in v3_pci_probe()
738 v3->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); in v3_pci_probe()
739 if (IS_ERR(v3->base)) in v3_pci_probe()
740 return PTR_ERR(v3->base); in v3_pci_probe()
743 * of the V3 controller itself, verify that this is the same in v3_pci_probe()
746 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) in v3_pci_probe()
748 readl(v3->base + V3_LB_IO_BASE), regs); in v3_pci_probe()
756 v3->config_mem = regs->start; in v3_pci_probe()
757 v3->config_base = devm_ioremap_resource(dev, regs); in v3_pci_probe()
758 if (IS_ERR(v3->config_base)) in v3_pci_probe()
759 return PTR_ERR(v3->config_base); in v3_pci_probe()
767 "PCIv3 error", v3); in v3_pci_probe()
776 * Unlock V3 registers, but only if they were previously locked. in v3_pci_probe()
778 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) in v3_pci_probe()
779 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); in v3_pci_probe()
782 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
784 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
787 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
789 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
792 val = readw(v3->base + V3_PCI_CFG); in v3_pci_probe()
794 writew(val, v3->base + V3_PCI_CFG); in v3_pci_probe()
797 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
802 writew(val, v3->base + V3_LB_CFG); in v3_pci_probe()
805 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
807 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
811 ret = v3_pci_setup_resource(v3, host, win); in v3_pci_probe()
817 ret = v3_pci_parse_map_dma_ranges(v3, np); in v3_pci_probe()
826 writel(0x00000000, v3->base + V3_PCI_IO_BASE); in v3_pci_probe()
834 writew(val, v3->base + V3_PCI_CFG); in v3_pci_probe()
837 * Set the V3 FIFO such that writes have higher priority than in v3_pci_probe()
845 v3->base + V3_FIFO_PRIORITY); in v3_pci_probe()
852 writeb(0, v3->base + V3_LB_ISTAT); in v3_pci_probe()
853 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
855 writew(val, v3->base + V3_LB_CFG); in v3_pci_probe()
857 v3->base + V3_LB_IMASK); in v3_pci_probe()
861 ret = v3_integrator_init(v3); in v3_pci_probe()
867 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
869 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
872 writeb(0, v3->base + V3_LB_ISTAT); in v3_pci_probe()
875 v3->base + V3_LB_IMASK); in v3_pci_probe()
878 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
880 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
885 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
887 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
894 .compatible = "v3,v360epc-pci",
901 .name = "pci-v3-semi",