Lines Matching refs:advk_readl
297 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() function
307 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
395 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
410 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
421 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
490 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
496 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
502 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
531 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
537 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
549 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
564 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
575 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
591 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
596 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
614 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
631 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
660 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
688 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
754 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
767 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
768 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
786 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
797 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) in advk_pci_bridge_emul_base_conf_read()
801 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
832 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_base_conf_write()
840 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
870 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
883 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
899 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
954 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
982 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
1040 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
1042 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
1044 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
1080 bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff; in advk_sw_pci_bridge_init()
1081 bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16; in advk_sw_pci_bridge_init()
1131 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1168 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1249 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1315 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_mask()
1329 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_unmask()
1401 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1415 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1570 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; in advk_pcie_handle_pme()
1598 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1599 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1621 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1622 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1625 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1626 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1668 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1937 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_remove()
1942 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_remove()
1975 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_remove()