Lines Matching +full:pcie +full:- +full:6
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
20 #include <linux/pci-ecam.h>
29 #include "../pci-bridge-emul.h"
31 /* PCIe core registers */
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
82 #define LINK_TRAINING_EN BIT(6)
93 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
124 /* PCIe window configuration */
139 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
153 #define OB_WIN_ATTR_NOSNOOP BIT(6)
215 /* PCIe core controller registers */
223 /* PCIe Central Interrupts Registers */
232 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
292 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
294 writel(val, pcie->base + reg); in advk_writel()
297 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
299 return readl(pcie->base + reg); in advk_readl()
302 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
307 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
312 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
314 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
315 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
319 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
322 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
323 * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle in advk_pcie_link_active()
329 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
333 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) in advk_pcie_link_training() argument
336 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
340 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_training()
347 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) in advk_pcie_wait_for_link() argument
353 if (advk_pcie_link_up(pcie)) in advk_pcie_wait_for_link()
359 return -ETIMEDOUT; in advk_pcie_wait_for_link()
362 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) in advk_pcie_wait_for_retrain() argument
367 if (advk_pcie_link_training(pcie)) in advk_pcie_wait_for_retrain()
373 static void advk_pcie_issue_perst(struct advk_pcie *pcie) in advk_pcie_issue_perst() argument
375 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
379 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
380 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
382 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
385 static void advk_pcie_train_link(struct advk_pcie *pcie) in advk_pcie_train_link() argument
387 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
392 * Setup PCIe rev / gen compliance based on device tree property in advk_pcie_train_link()
393 * 'max-link-speed' which also forces maximal link speed. in advk_pcie_train_link()
395 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
397 if (pcie->link_gen == 3) in advk_pcie_train_link()
399 else if (pcie->link_gen == 2) in advk_pcie_train_link()
403 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
406 * Set maximal link speed value also into PCIe Link Control 2 register. in advk_pcie_train_link()
410 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
412 if (pcie->link_gen == 3) in advk_pcie_train_link()
414 else if (pcie->link_gen == 2) in advk_pcie_train_link()
418 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
420 /* Enable link training after selecting PCIe generation */ in advk_pcie_train_link()
421 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
423 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
426 * Reset PCIe card via PERST# signal. Some cards are not detected in advk_pcie_train_link()
427 * during link training when they are in some non-initial state. in advk_pcie_train_link()
429 advk_pcie_issue_perst(pcie); in advk_pcie_train_link()
439 * So wait until PCIe link is up. Function advk_pcie_wait_for_link() in advk_pcie_train_link()
442 ret = advk_pcie_wait_for_link(pcie); in advk_pcie_train_link()
450 * Set PCIe address window register which could be used for memory
453 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
457 advk_writel(pcie, OB_WIN_ENABLE | in advk_pcie_set_ob_win()
459 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
460 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
461 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
462 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
463 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
464 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
467 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
469 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
470 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); in advk_pcie_disable_ob_win()
471 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); in advk_pcie_disable_ob_win()
472 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); in advk_pcie_disable_ob_win()
473 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); in advk_pcie_disable_ob_win()
474 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); in advk_pcie_disable_ob_win()
475 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); in advk_pcie_disable_ob_win()
478 static void advk_pcie_setup_hw(struct advk_pcie *pcie) in advk_pcie_setup_hw() argument
485 * Configure PCIe Reference clock. Direction is from the PCIe in advk_pcie_setup_hw()
487 * Reference clock differential signal off-chip and disable in advk_pcie_setup_hw()
488 * receiving off-chip differential signal. in advk_pcie_setup_hw()
490 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
493 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
496 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
499 advk_writel(pcie, reg, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
502 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
504 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
510 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround in advk_pcie_setup_hw()
514 advk_writel(pcie, reg, VENDOR_ID_REG); in advk_pcie_setup_hw()
524 * and is reported as Type 0. In range 0x10 - 0x34 it has totally in advk_pcie_setup_hw()
531 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
534 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
537 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
539 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
546 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in advk_pcie_setup_hw()
548 /* Set PCIe Device Control register */ in advk_pcie_setup_hw()
549 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
556 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
558 /* Program PCIe Control 2 to disable strict ordering */ in advk_pcie_setup_hw()
561 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
564 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
567 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
570 msi_addr = virt_to_phys(pcie); in advk_pcie_setup_hw()
571 advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); in advk_pcie_setup_hw()
572 advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); in advk_pcie_setup_hw()
575 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
577 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
580 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); in advk_pcie_setup_hw()
581 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_setup_hw()
582 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_setup_hw()
583 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_setup_hw()
586 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
587 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_setup_hw()
588 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); in advk_pcie_setup_hw()
591 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
593 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
596 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
598 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
602 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); in advk_pcie_setup_hw()
609 * the outbound transactions. Thus, PCIe address in advk_pcie_setup_hw()
614 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
616 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
620 * is not required to configure PCIe address for in advk_pcie_setup_hw()
623 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); in advk_pcie_setup_hw()
631 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
633 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_setup_hw()
636 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
637 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
640 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
641 advk_pcie_set_ob_win(pcie, i, in advk_pcie_setup_hw()
642 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
643 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
645 /* Disable remaining PCIe outbound windows */ in advk_pcie_setup_hw()
646 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
647 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_setup_hw()
649 advk_pcie_train_link(pcie); in advk_pcie_setup_hw()
652 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_rrs, u32 *val) in advk_pcie_check_pio_status() argument
654 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
660 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
683 ret = -EFAULT; in advk_pcie_check_pio_status()
688 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
695 ret = -EOPNOTSUPP; in advk_pcie_check_pio_status()
699 /* PCIe r6.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
705 * read-data value of 0001h for the Vendor ID field and in advk_pcie_check_pio_status()
716 /* PCIe r6.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
718 * must re-issue the Configuration Request as a new Request. in advk_pcie_check_pio_status()
721 * the Root Complex must re-issue the Configuration Request as in advk_pcie_check_pio_status()
729 * So return -EAGAIN and caller (pci-aardvark.c driver) will in advk_pcie_check_pio_status()
730 * re-issue request again up to the PIO_RETRY_CNT retries. in advk_pcie_check_pio_status()
733 ret = -EAGAIN; in advk_pcie_check_pio_status()
737 ret = -ECANCELED; in advk_pcie_check_pio_status()
741 ret = -EINVAL; in advk_pcie_check_pio_status()
749 str_posted = "Non-posted"; in advk_pcie_check_pio_status()
754 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
759 static int advk_pcie_wait_pio(struct advk_pcie *pcie) in advk_pcie_wait_pio() argument
761 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
767 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
768 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
775 return -ETIMEDOUT; in advk_pcie_wait_pio()
782 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read() local
786 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
795 __le32 *cfgspace = (__le32 *)&bridge->conf; in advk_pci_bridge_emul_base_conf_read()
797 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) in advk_pci_bridge_emul_base_conf_read()
801 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
818 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write() local
822 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_write()
827 * According to Figure 6-3: Pseudo Logic Diagram for Error in advk_pci_bridge_emul_base_conf_write()
828 * Message Controls in PCIe base specification, SERR# Enable bit in advk_pci_bridge_emul_base_conf_write()
832 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_base_conf_write()
837 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_base_conf_write()
840 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
845 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
858 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read() local
870 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
883 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
885 if (advk_pcie_link_training(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
887 if (advk_pcie_link_active(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
899 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
912 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write() local
916 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
918 advk_pcie_wait_for_retrain(pcie); in advk_pci_bridge_emul_pcie_conf_write()
922 u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); in advk_pci_bridge_emul_pcie_conf_write()
925 bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); in advk_pci_bridge_emul_pcie_conf_write()
938 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
950 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_ext_conf_read() local
954 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
982 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
994 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_ext_conf_write() local
1014 advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_write()
1032 * Initialize the configuration space of the PCI-to-PCI bridge
1033 * associated with the given PCIe interface.
1035 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) in advk_sw_pci_bridge_init() argument
1037 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
1039 bridge->conf.vendor = in advk_sw_pci_bridge_init()
1040 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
1041 bridge->conf.device = in advk_sw_pci_bridge_init()
1042 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
1043 bridge->conf.class_revision = in advk_sw_pci_bridge_init()
1044 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
1047 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
1048 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
1051 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
1052 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
1055 bridge->conf.intpin = PCI_INTERRUPT_INTA; in advk_sw_pci_bridge_init()
1058 * Aardvark HW provides PCIe Capability structure in version 2 and in advk_sw_pci_bridge_init()
1061 bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); in advk_sw_pci_bridge_init()
1073 bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN, in advk_sw_pci_bridge_init()
1075 bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); in advk_sw_pci_bridge_init()
1078 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_RRS_SV); in advk_sw_pci_bridge_init()
1080 bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff; in advk_sw_pci_bridge_init()
1081 bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16; in advk_sw_pci_bridge_init()
1082 bridge->has_pcie = true; in advk_sw_pci_bridge_init()
1083 bridge->pcie_start = PCIE_CORE_PCIEXP_CAP; in advk_sw_pci_bridge_init()
1084 bridge->data = pcie; in advk_sw_pci_bridge_init()
1085 bridge->ops = &advk_pci_bridge_emul_ops; in advk_sw_pci_bridge_init()
1090 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, in advk_pcie_valid_device() argument
1097 * If the link goes down after we check for link-up, we have a problem: in advk_pcie_valid_device()
1098 * if a PIO request is executed while link-down, the whole controller in advk_pcie_valid_device()
1099 * gets stuck in a non-functional state, and even after link comes up in advk_pcie_valid_device()
1100 * again, PIO requests won't work anymore, and a reset of the whole PCIe in advk_pcie_valid_device()
1104 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) in advk_pcie_valid_device()
1110 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) in advk_pcie_pio_is_running() argument
1112 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1118 * SError Interrupt on CPU0, code 0xbf000002 -- SError in advk_pcie_pio_is_running()
1119 * Kernel panic - not syncing: Asynchronous SError Interrupt in advk_pcie_pio_is_running()
1128 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: in advk_pcie_pio_is_running()
1129 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 in advk_pcie_pio_is_running()
1131 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1142 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf() local
1148 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_rd_conf()
1152 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1161 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1164 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_rd_conf()
1168 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1170 if (pci_is_root_bus(bus->parent)) in advk_pcie_rd_conf()
1174 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_rd_conf()
1177 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_rd_conf()
1178 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_rd_conf()
1179 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_rd_conf()
1182 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); in advk_pcie_rd_conf()
1187 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_rd_conf()
1188 advk_writel(pcie, 1, PIO_START); in advk_pcie_rd_conf()
1190 ret = advk_pcie_wait_pio(pcie); in advk_pcie_rd_conf()
1197 ret = advk_pcie_check_pio_status(pcie, allow_rrs, val); in advk_pcie_rd_conf()
1198 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_rd_conf()
1228 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf() local
1235 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_wr_conf()
1239 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1245 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_wr_conf()
1249 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1251 if (pci_is_root_bus(bus->parent)) in advk_pcie_wr_conf()
1255 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_wr_conf()
1258 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_wr_conf()
1259 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_wr_conf()
1260 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_wr_conf()
1265 data_strobe = GENMASK(size - 1, 0) << offset; in advk_pcie_wr_conf()
1268 advk_writel(pcie, reg, PIO_WR_DATA); in advk_pcie_wr_conf()
1271 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); in advk_pcie_wr_conf()
1276 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_wr_conf()
1277 advk_writel(pcie, 1, PIO_START); in advk_pcie_wr_conf()
1279 ret = advk_pcie_wait_pio(pcie); in advk_pcie_wr_conf()
1285 ret = advk_pcie_check_pio_status(pcie, false, NULL); in advk_pcie_wr_conf()
1286 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_wr_conf()
1299 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); in advk_msi_irq_compose_msi_msg() local
1300 phys_addr_t msi_addr = virt_to_phys(pcie); in advk_msi_irq_compose_msi_msg()
1302 msg->address_lo = lower_32_bits(msi_addr); in advk_msi_irq_compose_msi_msg()
1303 msg->address_hi = upper_32_bits(msi_addr); in advk_msi_irq_compose_msi_msg()
1304 msg->data = data->hwirq; in advk_msi_irq_compose_msi_msg()
1309 struct advk_pcie *pcie = d->domain->host_data; in advk_msi_irq_mask() local
1314 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); in advk_msi_irq_mask()
1315 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_mask()
1317 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); in advk_msi_irq_mask()
1318 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); in advk_msi_irq_mask()
1323 struct advk_pcie *pcie = d->domain->host_data; in advk_msi_irq_unmask() local
1328 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); in advk_msi_irq_unmask()
1329 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_unmask()
1331 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); in advk_msi_irq_unmask()
1332 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); in advk_msi_irq_unmask()
1358 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc() local
1361 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1362 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1364 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1366 return -ENOSPC; in advk_msi_irq_domain_alloc()
1371 domain->host_data, handle_simple_irq, in advk_msi_irq_domain_alloc()
1381 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free() local
1383 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1384 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); in advk_msi_irq_domain_free()
1385 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1395 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask() local
1400 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1401 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1403 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1404 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1409 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask() local
1414 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1415 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1417 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1418 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1424 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map() local
1427 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1429 irq_set_chip_data(virq, pcie); in advk_pcie_irq_map()
1440 .name = "advk-MSI",
1452 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_msi_irq_domain() argument
1454 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1456 raw_spin_lock_init(&pcie->msi_irq_lock); in advk_pcie_init_msi_irq_domain()
1457 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1459 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1461 &advk_msi_domain_ops, pcie); in advk_pcie_init_msi_irq_domain()
1462 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1463 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1465 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1468 pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1469 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1470 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1471 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1477 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_msi_irq_domain() argument
1479 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1480 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1483 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_irq_domain() argument
1485 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1486 struct device_node *node = dev->of_node; in advk_pcie_init_irq_domain()
1491 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1495 dev_err(dev, "No PCIe Intc node found\n"); in advk_pcie_init_irq_domain()
1496 return -ENODEV; in advk_pcie_init_irq_domain()
1499 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1501 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", in advk_pcie_init_irq_domain()
1503 if (!irq_chip->name) { in advk_pcie_init_irq_domain()
1504 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1508 irq_chip->irq_mask = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1509 irq_chip->irq_unmask = advk_pcie_irq_unmask; in advk_pcie_init_irq_domain()
1511 pcie->irq_domain = in advk_pcie_init_irq_domain()
1513 &advk_pcie_irq_domain_ops, pcie); in advk_pcie_init_irq_domain()
1514 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1516 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1525 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_irq_domain() argument
1527 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1531 .name = "advk-RP",
1537 struct advk_pcie *pcie = h->host_data; in advk_pcie_rp_irq_map() local
1540 irq_set_chip_data(virq, pcie); in advk_pcie_rp_irq_map()
1550 static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_rp_irq_domain() argument
1552 pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1, in advk_pcie_init_rp_irq_domain()
1554 pcie); in advk_pcie_init_rp_irq_domain()
1555 if (!pcie->rp_irq_domain) { in advk_pcie_init_rp_irq_domain()
1556 dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n"); in advk_pcie_init_rp_irq_domain()
1557 return -ENOMEM; in advk_pcie_init_rp_irq_domain()
1563 static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_rp_irq_domain() argument
1565 irq_domain_remove(pcie->rp_irq_domain); in advk_pcie_remove_rp_irq_domain()
1568 static void advk_pcie_handle_pme(struct advk_pcie *pcie) in advk_pcie_handle_pme() argument
1570 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; in advk_pcie_handle_pme()
1572 advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); in advk_pcie_handle_pme()
1579 if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) { in advk_pcie_handle_pme()
1580 pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME); in advk_pcie_handle_pme()
1584 * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0. in advk_pcie_handle_pme()
1586 if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) in advk_pcie_handle_pme()
1589 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) in advk_pcie_handle_pme()
1590 dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); in advk_pcie_handle_pme()
1594 static void advk_pcie_handle_msi(struct advk_pcie *pcie) in advk_pcie_handle_msi() argument
1598 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1599 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1606 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1607 if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL) in advk_pcie_handle_msi()
1608 dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); in advk_pcie_handle_msi()
1611 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, in advk_pcie_handle_msi()
1615 static void advk_pcie_handle_int(struct advk_pcie *pcie) in advk_pcie_handle_int() argument
1621 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1622 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1625 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1626 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1631 advk_pcie_handle_pme(pcie); in advk_pcie_handle_int()
1635 advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG); in advk_pcie_handle_int()
1639 * PCIe interrupt 0 in advk_pcie_handle_int()
1641 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) in advk_pcie_handle_int()
1642 dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); in advk_pcie_handle_int()
1647 advk_pcie_handle_msi(pcie); in advk_pcie_handle_int()
1654 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), in advk_pcie_handle_int()
1657 if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL) in advk_pcie_handle_int()
1658 dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", in advk_pcie_handle_int()
1665 struct advk_pcie *pcie = arg; in advk_pcie_irq_handler() local
1668 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1672 advk_pcie_handle_int(pcie); in advk_pcie_irq_handler()
1675 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1682 struct advk_pcie *pcie = dev->bus->sysdata; in advk_pcie_map_irq() local
1689 if (pci_is_root_bus(dev->bus)) in advk_pcie_map_irq()
1690 return irq_create_mapping(pcie->rp_irq_domain, pin - 1); in advk_pcie_map_irq()
1695 static void advk_pcie_disable_phy(struct advk_pcie *pcie) in advk_pcie_disable_phy() argument
1697 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1698 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1701 static int advk_pcie_enable_phy(struct advk_pcie *pcie) in advk_pcie_enable_phy() argument
1705 if (!pcie->phy) in advk_pcie_enable_phy()
1708 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1712 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1714 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1718 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1720 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1727 static int advk_pcie_setup_phy(struct advk_pcie *pcie) in advk_pcie_setup_phy() argument
1729 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1730 struct device_node *node = dev->of_node; in advk_pcie_setup_phy()
1733 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1734 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1735 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1738 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1739 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1740 pcie->phy = NULL; in advk_pcie_setup_phy()
1744 ret = advk_pcie_enable_phy(pcie); in advk_pcie_setup_phy()
1753 struct device *dev = &pdev->dev; in advk_pcie_probe()
1754 struct advk_pcie *pcie; in advk_pcie_probe() local
1761 return -ENOMEM; in advk_pcie_probe()
1763 pcie = pci_host_bridge_priv(bridge); in advk_pcie_probe()
1764 pcie->pdev = pdev; in advk_pcie_probe()
1765 platform_set_drvdata(pdev, pcie); in advk_pcie_probe()
1767 resource_list_for_each_entry(entry, &bridge->windows) { in advk_pcie_probe()
1768 resource_size_t start = entry->res->start; in advk_pcie_probe()
1769 resource_size_t size = resource_size(entry->res); in advk_pcie_probe()
1770 unsigned long type = resource_type(entry->res); in advk_pcie_probe()
1774 * Aardvark hardware allows to configure also PCIe window in advk_pcie_probe()
1777 * not use PCIe window configuration. in advk_pcie_probe()
1787 if (type == IORESOURCE_MEM && entry->offset == 0) in advk_pcie_probe()
1791 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1794 * So every PCIe window size must be a power of two and every start in advk_pcie_probe()
1799 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1801 win_size = (1ULL << (fls64(size)-1)) | in advk_pcie_probe()
1808 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1809 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1813 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1814 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1816 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1817 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1819 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1820 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1822 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1826 size -= win_size; in advk_pcie_probe()
1827 pcie->wins_count++; in advk_pcie_probe()
1831 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1832 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1833 (unsigned long long)entry->res->start, in advk_pcie_probe()
1834 (unsigned long long)entry->res->end + 1); in advk_pcie_probe()
1835 return -EINVAL; in advk_pcie_probe()
1839 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1840 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1841 return PTR_ERR(pcie->base); in advk_pcie_probe()
1848 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1849 pcie); in advk_pcie_probe()
1855 pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in advk_pcie_probe()
1856 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1858 if (ret != -EPROBE_DEFER) in advk_pcie_probe()
1859 dev_err(dev, "Failed to get reset-gpio: %i\n", ret); in advk_pcie_probe()
1863 ret = gpiod_set_consumer_name(pcie->reset_gpio, "pcie1-reset"); in advk_pcie_probe()
1869 ret = of_pci_get_max_link_speed(dev->of_node); in advk_pcie_probe()
1871 pcie->link_gen = 3; in advk_pcie_probe()
1873 pcie->link_gen = ret; in advk_pcie_probe()
1875 ret = advk_pcie_setup_phy(pcie); in advk_pcie_probe()
1879 advk_pcie_setup_hw(pcie); in advk_pcie_probe()
1881 ret = advk_sw_pci_bridge_init(pcie); in advk_pcie_probe()
1887 ret = advk_pcie_init_irq_domain(pcie); in advk_pcie_probe()
1893 ret = advk_pcie_init_msi_irq_domain(pcie); in advk_pcie_probe()
1896 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1900 ret = advk_pcie_init_rp_irq_domain(pcie); in advk_pcie_probe()
1903 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1904 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1908 bridge->sysdata = pcie; in advk_pcie_probe()
1909 bridge->ops = &advk_pcie_ops; in advk_pcie_probe()
1910 bridge->map_irq = advk_pcie_map_irq; in advk_pcie_probe()
1914 advk_pcie_remove_rp_irq_domain(pcie); in advk_pcie_probe()
1915 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1916 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1925 struct advk_pcie *pcie = platform_get_drvdata(pdev); in advk_pcie_remove() local
1926 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in advk_pcie_remove()
1932 pci_stop_root_bus(bridge->bus); in advk_pcie_remove()
1933 pci_remove_root_bus(bridge->bus); in advk_pcie_remove()
1937 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_remove()
1939 advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_remove()
1942 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_remove()
1944 advk_writel(pcie, val, PCIE_CORE_CTRL2_REG); in advk_pcie_remove()
1947 advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG); in advk_pcie_remove()
1948 advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG); in advk_pcie_remove()
1951 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); in advk_pcie_remove()
1952 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); in advk_pcie_remove()
1953 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_remove()
1954 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG); in advk_pcie_remove()
1957 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); in advk_pcie_remove()
1958 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_remove()
1959 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_remove()
1960 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_remove()
1963 advk_pcie_remove_rp_irq_domain(pcie); in advk_pcie_remove()
1964 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_remove()
1965 advk_pcie_remove_irq_domain(pcie); in advk_pcie_remove()
1968 pci_bridge_emul_cleanup(&pcie->bridge); in advk_pcie_remove()
1970 /* Assert PERST# signal which prepares PCIe card for power down */ in advk_pcie_remove()
1971 if (pcie->reset_gpio) in advk_pcie_remove()
1972 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_remove()
1975 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_remove()
1977 advk_writel(pcie, val, PCIE_CORE_CTRL0_REG); in advk_pcie_remove()
1981 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_remove()
1984 advk_pcie_disable_phy(pcie); in advk_pcie_remove()
1988 { .compatible = "marvell,armada-3700-pcie", },
1995 .name = "advk-pcie",
2003 MODULE_DESCRIPTION("Aardvark PCIe controller");