363 	u32 val, status_l0, status_l1;  in tegra_pcie_rp_irq_handler()  local
368 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_rp_irq_handler()
369 		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_rp_irq_handler()
371 		    status_l1 & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {  in tegra_pcie_rp_irq_handler()
388 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);  in tegra_pcie_rp_irq_handler()
389 		if (status_l1 & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {  in tegra_pcie_rp_irq_handler()
395 		if (status_l1 & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {  in tegra_pcie_rp_irq_handler()
414 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);  in tegra_pcie_rp_irq_handler()
416 		if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {  in tegra_pcie_rp_irq_handler()
420 		if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {  in tegra_pcie_rp_irq_handler()
424 		if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {  in tegra_pcie_rp_irq_handler()
521 	u32 status_l0, status_l1, link_status;  in tegra_pcie_ep_hard_irq()  local
525 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_ep_hard_irq()
526 		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_ep_hard_irq()
528 		if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)  in tegra_pcie_ep_hard_irq()
531 		if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {  in tegra_pcie_ep_hard_irq()
544 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);  in tegra_pcie_ep_hard_irq()
545 		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);  in tegra_pcie_ep_hard_irq()
547 		if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)  in tegra_pcie_ep_hard_irq()