48 #define APPL_CTRL				0x4  macro
457 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_hot_rst_done()
459 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_hot_rst_done()
969 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
971 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
1004 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
1006 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
1412 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1418 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_config_controller()
1436 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1437 	appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);  in tegra_pcie_config_controller()
1600 		data = readl(pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1602 		writel(data, pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1695 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1697 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1813 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1816 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1906 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1908 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
2320 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2324 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2390 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_resume_early()
2396 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_resume_early()