Lines Matching +full:r8a779f0 +full:- +full:pcie
1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
4 * Copyright (C) 2022-2023 Renesas Electronics Corporation
6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
7 * provided, to initialize the PHY. Otherwise, the PCIe controller will not
24 #include "pcie-designware.h"
26 /* Renesas-specific */
27 /* PCIe Mode Setting Register 0 */
34 /* PCIe Interrupt Status 0 */
37 /* PCIe Interrupt Status 0 Enable */
43 /* PCIe DMA Interrupt Status Enable */
53 /* PCIe Reset Control Register 1 */
58 /* PCIe Power Management Control */
95 val = readl(rcar->base + PCIEINTSTS0); in rcar_gen4_pcie_link_up()
103 * -ETIMEDOUT.
125 return -ETIMEDOUT; in rcar_gen4_pcie_speed_change()
137 if (rcar->drvdata->ltssm_control) { in rcar_gen4_pcie_start_link()
138 ret = rcar->drvdata->ltssm_control(rcar, true); in rcar_gen4_pcie_start_link()
145 * is PCIe Gen2 or higher. in rcar_gen4_pcie_start_link()
147 changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1; in rcar_gen4_pcie_start_link()
150 * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained. in rcar_gen4_pcie_start_link()
151 * So, this needs remaining times for up to PCIe Gen4 if RC mode. in rcar_gen4_pcie_start_link()
153 if (changes && rcar->drvdata->mode == DW_PCIE_RC_TYPE) in rcar_gen4_pcie_start_link()
154 changes--; in rcar_gen4_pcie_start_link()
169 if (rcar->drvdata->ltssm_control) in rcar_gen4_pcie_stop_link()
170 rcar->drvdata->ltssm_control(rcar, false); in rcar_gen4_pcie_stop_link()
175 struct dw_pcie *dw = &rcar->dw; in rcar_gen4_pcie_common_init()
179 ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); in rcar_gen4_pcie_common_init()
181 dev_err(dw->dev, "Enabling core clocks failed\n"); in rcar_gen4_pcie_common_init()
185 if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) in rcar_gen4_pcie_common_init()
186 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc); in rcar_gen4_pcie_common_init()
188 val = readl(rcar->base + PCIEMSR0); in rcar_gen4_pcie_common_init()
189 if (rcar->drvdata->mode == DW_PCIE_RC_TYPE) { in rcar_gen4_pcie_common_init()
191 } else if (rcar->drvdata->mode == DW_PCIE_EP_TYPE) { in rcar_gen4_pcie_common_init()
194 ret = -EINVAL; in rcar_gen4_pcie_common_init()
198 if (dw->num_lanes < 4) in rcar_gen4_pcie_common_init()
201 writel(val, rcar->base + PCIEMSR0); in rcar_gen4_pcie_common_init()
203 ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc); in rcar_gen4_pcie_common_init()
207 if (rcar->drvdata->additional_common_init) in rcar_gen4_pcie_common_init()
208 rcar->drvdata->additional_common_init(rcar); in rcar_gen4_pcie_common_init()
213 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); in rcar_gen4_pcie_common_init()
220 struct dw_pcie *dw = &rcar->dw; in rcar_gen4_pcie_common_deinit()
222 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc); in rcar_gen4_pcie_common_deinit()
223 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); in rcar_gen4_pcie_common_deinit()
228 struct device *dev = rcar->dw.dev; in rcar_gen4_pcie_prepare()
243 struct device *dev = rcar->dw.dev; in rcar_gen4_pcie_unprepare()
251 rcar->phy_base = devm_platform_ioremap_resource_byname(rcar->pdev, "phy"); in rcar_gen4_pcie_get_resources()
252 if (IS_ERR(rcar->phy_base)) in rcar_gen4_pcie_get_resources()
253 return PTR_ERR(rcar->phy_base); in rcar_gen4_pcie_get_resources()
255 /* Renesas-specific registers */ in rcar_gen4_pcie_get_resources()
256 rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app"); in rcar_gen4_pcie_get_resources()
258 return PTR_ERR_OR_ZERO(rcar->base); in rcar_gen4_pcie_get_resources()
269 struct device *dev = &pdev->dev; in rcar_gen4_pcie_alloc()
274 return ERR_PTR(-ENOMEM); in rcar_gen4_pcie_alloc()
276 rcar->dw.ops = &dw_pcie_ops; in rcar_gen4_pcie_alloc()
277 rcar->dw.dev = dev; in rcar_gen4_pcie_alloc()
278 rcar->pdev = pdev; in rcar_gen4_pcie_alloc()
279 rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL; in rcar_gen4_pcie_alloc()
280 dw_pcie_cap_set(&rcar->dw, REQ_RES); in rcar_gen4_pcie_alloc()
294 gpiod_set_value_cansleep(dw->pe_rst, 1); in rcar_gen4_pcie_host_init()
301 * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode in rcar_gen4_pcie_host_init()
302 * Rev.5.20a and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a, we in rcar_gen4_pcie_host_init()
310 val = readl(rcar->base + PCIEINTSTS0EN); in rcar_gen4_pcie_host_init()
312 writel(val, rcar->base + PCIEINTSTS0EN); in rcar_gen4_pcie_host_init()
316 gpiod_set_value_cansleep(dw->pe_rst, 0); in rcar_gen4_pcie_host_init()
326 gpiod_set_value_cansleep(dw->pe_rst, 1); in rcar_gen4_pcie_host_deinit()
337 struct dw_pcie_rp *pp = &rcar->dw.pp; in rcar_gen4_add_dw_pcie_rp()
340 return -ENODEV; in rcar_gen4_add_dw_pcie_rp()
342 pp->num_vectors = MAX_MSI_IRQS; in rcar_gen4_add_dw_pcie_rp()
343 pp->ops = &rcar_gen4_pcie_host_ops; in rcar_gen4_add_dw_pcie_rp()
350 dw_pcie_host_deinit(&rcar->dw.pp); in rcar_gen4_remove_dw_pcie_rp()
364 writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN); in rcar_gen4_pcie_ep_pre_init()
378 writel(0, rcar->base + PCIEDMAINTSTSEN); in rcar_gen4_pcie_ep_deinit()
393 dev_err(dw->dev, "Unknown IRQ type\n"); in rcar_gen4_pcie_ep_raise_irq()
394 return -EINVAL; in rcar_gen4_pcie_ep_raise_irq()
439 struct dw_pcie_ep *ep = &rcar->dw.ep; in rcar_gen4_add_dw_pcie_ep()
440 struct device *dev = rcar->dw.dev; in rcar_gen4_add_dw_pcie_ep()
444 return -ENODEV; in rcar_gen4_add_dw_pcie_ep()
446 ep->ops = &pcie_ep_ops; in rcar_gen4_add_dw_pcie_ep()
461 pci_epc_init_notify(ep->epc); in rcar_gen4_add_dw_pcie_ep()
468 dw_pcie_ep_deinit(&rcar->dw.ep); in rcar_gen4_remove_dw_pcie_ep()
475 rcar->drvdata = of_device_get_match_data(&rcar->pdev->dev); in rcar_gen4_add_dw_pcie()
476 if (!rcar->drvdata) in rcar_gen4_add_dw_pcie()
477 return -EINVAL; in rcar_gen4_add_dw_pcie()
479 switch (rcar->drvdata->mode) { in rcar_gen4_add_dw_pcie()
485 return -EINVAL; in rcar_gen4_add_dw_pcie()
520 switch (rcar->drvdata->mode) { in rcar_gen4_remove_dw_pcie()
544 val = readl(rcar->base + PCIERSTCTRL1); in r8a779f0_pcie_ltssm_control()
550 * Since the datasheet of R-Car doesn't mention how to assert in r8a779f0_pcie_ltssm_control()
552 * hang-up issue happened in the dw_edma_core_off() when in r8a779f0_pcie_ltssm_control()
557 writel(val, rcar->base + PCIERSTCTRL1); in r8a779f0_pcie_ltssm_control()
564 struct dw_pcie *dw = &rcar->dw; in rcar_gen4_pcie_additional_common_init()
569 if (dw->num_lanes < 4) in rcar_gen4_pcie_additional_common_init()
573 val = readl(rcar->base + PCIEPWRMNGCTRL); in rcar_gen4_pcie_additional_common_init()
575 writel(val, rcar->base + PCIEPWRMNGCTRL); in rcar_gen4_pcie_additional_common_init()
583 tmp = readl(rcar->phy_base + offset); in rcar_gen4_pcie_phy_reg_update_bits()
586 writel(tmp, rcar->phy_base + offset); in rcar_gen4_pcie_phy_reg_update_bits()
591 * write. If read returns non-zero value, then this function returns -EAGAIN
598 struct dw_pcie *dw = &rcar->dw; in rcar_gen4_pcie_reg_test_bit()
601 return -EAGAIN; in rcar_gen4_pcie_reg_test_bit()
615 struct dw_pcie *dw = &rcar->dw; in rcar_gen4_pcie_download_phy_firmware()
621 ret = request_firmware(&fw, RCAR_GEN4_PCIE_FIRMWARE_NAME, dw->dev); in rcar_gen4_pcie_download_phy_firmware()
623 dev_err(dw->dev, "Failed to load firmware (%s): %d\n", in rcar_gen4_pcie_download_phy_firmware()
628 for (i = 0; i < (fw->size / 2); i++) { in rcar_gen4_pcie_download_phy_firmware()
629 data = fw->data[(i * 2) + 1] << 8 | fw->data[i * 2]; in rcar_gen4_pcie_download_phy_firmware()
636 if (!(--timeout)) { in rcar_gen4_pcie_download_phy_firmware()
637 ret = -ETIMEDOUT; in rcar_gen4_pcie_download_phy_firmware()
654 if (!(--timeout)) { in rcar_gen4_pcie_download_phy_firmware()
655 ret = -ETIMEDOUT; in rcar_gen4_pcie_download_phy_firmware()
670 struct dw_pcie *dw = &rcar->dw; in rcar_gen4_pcie_ltssm_control()
675 val = readl(rcar->base + PCIERSTCTRL1); in rcar_gen4_pcie_ltssm_control()
677 writel(val, rcar->base + PCIERSTCTRL1); in rcar_gen4_pcie_ltssm_control()
686 val = readl(rcar->base + PCIEMSR0); in rcar_gen4_pcie_ltssm_control()
688 writel(val, rcar->base + PCIEMSR0); in rcar_gen4_pcie_ltssm_control()
691 * The R-Car Gen4 datasheet doesn't describe the PHY registers' name. in rcar_gen4_pcie_ltssm_control()
709 val = readl(rcar->base + PCIERSTCTRL1); in rcar_gen4_pcie_ltssm_control()
711 writel(val, rcar->base + PCIERSTCTRL1); in rcar_gen4_pcie_ltssm_control()
713 ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, !(val & BIT(18)), 100, 10000); in rcar_gen4_pcie_ltssm_control()
721 val = readl(rcar->base + PCIERSTCTRL1); in rcar_gen4_pcie_ltssm_control()
723 writel(val, rcar->base + PCIERSTCTRL1); in rcar_gen4_pcie_ltssm_control()
752 .compatible = "renesas,r8a779f0-pcie",
756 .compatible = "renesas,r8a779f0-pcie-ep",
760 .compatible = "renesas,rcar-gen4-pcie",
764 .compatible = "renesas,rcar-gen4-pcie-ep",
773 .name = "pcie-rcar-gen4",
782 MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe controller driver");