Lines Matching full:pcie
3 * Qualcomm PCIe root complex driver
28 #include <linux/phy/pcie.h>
37 #include "pcie-designware.h"
38 #include "pcie-qcom-common.h"
243 int (*get_resources)(struct qcom_pcie *pcie);
244 int (*init)(struct qcom_pcie *pcie);
245 int (*post_init)(struct qcom_pcie *pcie);
246 void (*host_post_init)(struct qcom_pcie *pcie);
247 void (*deinit)(struct qcom_pcie *pcie);
248 void (*ltssm_enable)(struct qcom_pcie *pcie);
249 int (*config_sid)(struct qcom_pcie *pcie);
254 * @ops: qcom PCIe ops structure
282 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
284 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
288 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) in qcom_ep_reset_deassert() argument
292 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
298 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_start_link() local
306 if (pcie->cfg->ops->ltssm_enable) in qcom_pcie_start_link()
307 pcie->cfg->ops->ltssm_enable(pcie); in qcom_pcie_start_link()
314 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_clear_aspm_l0s() local
318 if (!pcie->cfg->no_l0s) in qcom_pcie_clear_aspm_l0s()
346 static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_base() argument
348 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_base()
355 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_base()
357 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_base()
362 static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_atu_base() argument
364 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_atu_base()
372 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
374 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
378 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
380 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
384 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); in qcom_pcie_configure_dbi_atu_base()
385 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_atu_base()
390 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_1_0_ltssm_enable() argument
395 val = readl(pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
397 writel(val, pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
400 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_1_0() argument
402 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_get_resources_2_1_0()
403 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_1_0()
405 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); in qcom_pcie_get_resources_2_1_0()
438 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_1_0() argument
440 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_deinit_2_1_0()
445 writel(1, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_deinit_2_1_0()
450 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_1_0() argument
452 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_init_2_1_0()
453 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_1_0()
457 /* reset the PCIe interface as uboot can leave it undefined state */ in qcom_pcie_init_2_1_0()
480 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_1_0() argument
482 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_post_init_2_1_0()
483 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_1_0()
489 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_1_0()
490 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
492 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
498 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || in qcom_pcie_post_init_2_1_0()
499 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { in qcom_pcie_post_init_2_1_0()
503 pcie->parf + PARF_PCS_DEEMPH); in qcom_pcie_post_init_2_1_0()
506 pcie->parf + PARF_PCS_SWING); in qcom_pcie_post_init_2_1_0()
507 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); in qcom_pcie_post_init_2_1_0()
510 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { in qcom_pcie_post_init_2_1_0()
512 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
515 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
519 val = readl(pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
521 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) in qcom_pcie_post_init_2_1_0()
524 writel(val, pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
535 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_1_0()
540 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_1_0_0() argument
542 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_get_resources_1_0_0()
543 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_1_0_0()
560 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_1_0_0() argument
562 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_deinit_1_0_0()
569 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_init_1_0_0() argument
571 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_init_1_0_0()
572 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_1_0_0()
604 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_1_0_0() argument
606 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_1_0_0()
609 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
612 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
615 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_1_0_0()
620 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_3_2_ltssm_enable() argument
625 val = readl(pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
627 writel(val, pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
630 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_2() argument
632 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_get_resources_2_3_2()
633 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_2()
653 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_2() argument
655 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_deinit_2_3_2()
661 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_2() argument
663 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_init_2_3_2()
664 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_2()
684 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_2() argument
688 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_3_2()
689 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
691 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
693 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_2_3_2()
696 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
698 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
700 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
702 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
704 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
706 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
708 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_3_2()
713 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_4_0() argument
715 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_get_resources_2_4_0()
716 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_4_0()
718 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); in qcom_pcie_get_resources_2_4_0()
749 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_4_0() argument
751 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_deinit_2_4_0()
757 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_4_0() argument
759 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_init_2_4_0()
760 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_4_0()
789 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_3() argument
791 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_get_resources_2_3_3()
792 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_3()
817 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_3() argument
819 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_deinit_2_3_3()
824 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_3() argument
826 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_init_2_3_3()
827 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_3()
869 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_3() argument
871 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_3_3()
875 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
877 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
879 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_3_3()
884 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_3()
885 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_3_3()
905 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_7_0() argument
907 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_get_resources_2_7_0()
908 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_7_0()
932 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_7_0() argument
934 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_init_2_7_0()
935 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_7_0()
967 /* configure PCIe to RC mode */ in qcom_pcie_init_2_7_0()
968 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_init_2_7_0()
970 /* enable PCIe clocks and resets */ in qcom_pcie_init_2_7_0()
971 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
973 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
975 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_init_2_7_0()
978 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
980 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
982 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
984 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
987 val = readl(pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
989 writel(val, pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
991 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
993 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
1004 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_7_0() argument
1006 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; in qcom_pcie_post_init_2_7_0()
1010 pcie->parf + PARF_NO_SNOOP_OVERIDE); in qcom_pcie_post_init_2_7_0()
1012 qcom_pcie_clear_aspm_l0s(pcie->pci); in qcom_pcie_post_init_2_7_0()
1013 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_7_0()
1030 static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_host_post_init_2_7_0() argument
1032 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_host_post_init_2_7_0()
1037 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_7_0() argument
1039 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_deinit_2_7_0()
1046 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) in qcom_pcie_config_sid_1_9_0() argument
1055 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; in qcom_pcie_config_sid_1_9_0()
1056 struct device *dev = pcie->pci->dev; in qcom_pcie_config_sid_1_9_0()
1067 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1069 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1122 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_9_0() argument
1124 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_get_resources_2_9_0()
1125 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_9_0()
1141 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_9_0() argument
1143 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_deinit_2_9_0()
1148 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_9_0() argument
1150 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_init_2_9_0()
1151 struct device *dev = pcie->pci->dev; in qcom_pcie_init_2_9_0()
1177 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_9_0() argument
1179 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_9_0()
1184 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1186 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1188 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_9_0()
1190 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_post_init_2_9_0()
1192 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_9_0()
1200 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_9_0()
1202 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_9_0()
1218 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); in qcom_pcie_post_init_2_9_0()
1234 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_init() local
1237 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1239 ret = pcie->cfg->ops->init(pcie); in qcom_pcie_host_init()
1243 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); in qcom_pcie_host_init()
1247 ret = phy_power_on(pcie->phy); in qcom_pcie_host_init()
1251 if (pcie->cfg->ops->post_init) { in qcom_pcie_host_init()
1252 ret = pcie->cfg->ops->post_init(pcie); in qcom_pcie_host_init()
1257 qcom_ep_reset_deassert(pcie); in qcom_pcie_host_init()
1259 if (pcie->cfg->ops->config_sid) { in qcom_pcie_host_init()
1260 ret = pcie->cfg->ops->config_sid(pcie); in qcom_pcie_host_init()
1268 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1270 phy_power_off(pcie->phy); in qcom_pcie_host_init()
1272 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_init()
1280 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_deinit() local
1282 qcom_ep_reset_assert(pcie); in qcom_pcie_host_deinit()
1283 phy_power_off(pcie->phy); in qcom_pcie_host_deinit()
1284 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_deinit()
1290 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_post_init() local
1292 if (pcie->cfg->ops->host_post_init) in qcom_pcie_host_post_init()
1293 pcie->cfg->ops->host_post_init(pcie); in qcom_pcie_host_post_init()
1423 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) in qcom_pcie_icc_init() argument
1425 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_init()
1428 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); in qcom_pcie_icc_init()
1429 if (IS_ERR(pcie->icc_mem)) in qcom_pcie_icc_init()
1430 return PTR_ERR(pcie->icc_mem); in qcom_pcie_icc_init()
1432 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); in qcom_pcie_icc_init()
1433 if (IS_ERR(pcie->icc_cpu)) in qcom_pcie_icc_init()
1434 return PTR_ERR(pcie->icc_cpu); in qcom_pcie_icc_init()
1440 * for the pcie-mem path. in qcom_pcie_icc_init()
1442 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); in qcom_pcie_icc_init()
1444 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_init()
1450 * Since the CPU-PCIe path is only used for activities like register in qcom_pcie_icc_init()
1455 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); in qcom_pcie_icc_init()
1457 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", in qcom_pcie_icc_init()
1459 icc_set_bw(pcie->icc_mem, 0, 0); in qcom_pcie_icc_init()
1466 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) in qcom_pcie_icc_opp_update() argument
1469 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_opp_update()
1484 if (pcie->icc_mem) { in qcom_pcie_icc_opp_update()
1485 ret = icc_set_bw(pcie->icc_mem, 0, in qcom_pcie_icc_opp_update()
1488 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_opp_update()
1491 } else if (pcie->use_pm_opp) { in qcom_pcie_icc_opp_update()
1511 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); in qcom_pcie_link_transition_count() local
1514 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); in qcom_pcie_link_transition_count()
1517 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); in qcom_pcie_link_transition_count()
1520 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); in qcom_pcie_link_transition_count()
1523 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); in qcom_pcie_link_transition_count()
1526 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); in qcom_pcie_link_transition_count()
1531 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) in qcom_pcie_init_debugfs() argument
1533 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_debugfs()
1541 pcie->debugfs = debugfs_create_dir(name, NULL); in qcom_pcie_init_debugfs()
1542 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, in qcom_pcie_init_debugfs()
1548 struct qcom_pcie *pcie = data; in qcom_pcie_global_irq_thread() local
1549 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_global_irq_thread()
1550 struct device *dev = pcie->pci->dev; in qcom_pcie_global_irq_thread()
1551 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); in qcom_pcie_global_irq_thread()
1553 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); in qcom_pcie_global_irq_thread()
1575 struct qcom_pcie *pcie; in qcom_pcie_probe() local
1588 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in qcom_pcie_probe()
1589 if (!pcie) in qcom_pcie_probe()
1605 pcie->pci = pci; in qcom_pcie_probe()
1607 pcie->cfg = pcie_cfg; in qcom_pcie_probe()
1609 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); in qcom_pcie_probe()
1610 if (IS_ERR(pcie->reset)) { in qcom_pcie_probe()
1611 ret = PTR_ERR(pcie->reset); in qcom_pcie_probe()
1615 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); in qcom_pcie_probe()
1616 if (IS_ERR(pcie->parf)) { in qcom_pcie_probe()
1617 ret = PTR_ERR(pcie->parf); in qcom_pcie_probe()
1621 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); in qcom_pcie_probe()
1622 if (IS_ERR(pcie->elbi)) { in qcom_pcie_probe()
1623 ret = PTR_ERR(pcie->elbi); in qcom_pcie_probe()
1630 pcie->mhi = devm_ioremap_resource(dev, res); in qcom_pcie_probe()
1631 if (IS_ERR(pcie->mhi)) { in qcom_pcie_probe()
1632 ret = PTR_ERR(pcie->mhi); in qcom_pcie_probe()
1637 pcie->phy = devm_phy_optional_get(dev, "pciephy"); in qcom_pcie_probe()
1638 if (IS_ERR(pcie->phy)) { in qcom_pcie_probe()
1639 ret = PTR_ERR(pcie->phy); in qcom_pcie_probe()
1651 * Before the PCIe link is initialized, vote for highest OPP in the OPP in qcom_pcie_probe()
1675 pcie->use_pm_opp = true; in qcom_pcie_probe()
1678 ret = qcom_pcie_icc_init(pcie); in qcom_pcie_probe()
1683 ret = pcie->cfg->ops->get_resources(pcie); in qcom_pcie_probe()
1689 ret = phy_init(pcie->phy); in qcom_pcie_probe()
1693 platform_set_drvdata(pdev, pcie); in qcom_pcie_probe()
1712 IRQF_ONESHOT, name, pcie); in qcom_pcie_probe()
1719 writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); in qcom_pcie_probe()
1722 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_probe()
1724 if (pcie->mhi) in qcom_pcie_probe()
1725 qcom_pcie_init_debugfs(pcie); in qcom_pcie_probe()
1732 phy_exit(pcie->phy); in qcom_pcie_probe()
1742 struct qcom_pcie *pcie = dev_get_drvdata(dev); in qcom_pcie_suspend_noirq() local
1749 if (pcie->icc_mem) { in qcom_pcie_suspend_noirq()
1750 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); in qcom_pcie_suspend_noirq()
1753 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_suspend_noirq()
1760 * Turn OFF the resources only for controllers without active PCIe in qcom_pcie_suspend_noirq()
1764 * Turning OFF the resources for controllers with active PCIe devices in qcom_pcie_suspend_noirq()
1766 * as kernel tries to access the PCIe devices config space for masking in qcom_pcie_suspend_noirq()
1774 if (!dw_pcie_link_up(pcie->pci)) { in qcom_pcie_suspend_noirq()
1775 qcom_pcie_host_deinit(&pcie->pci->pp); in qcom_pcie_suspend_noirq()
1776 pcie->suspended = true; in qcom_pcie_suspend_noirq()
1780 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. in qcom_pcie_suspend_noirq()
1782 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC in qcom_pcie_suspend_noirq()
1786 ret = icc_disable(pcie->icc_cpu); in qcom_pcie_suspend_noirq()
1788 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_suspend_noirq()
1790 if (pcie->use_pm_opp) in qcom_pcie_suspend_noirq()
1791 dev_pm_opp_set_opp(pcie->pci->dev, NULL); in qcom_pcie_suspend_noirq()
1798 struct qcom_pcie *pcie = dev_get_drvdata(dev); in qcom_pcie_resume_noirq() local
1802 ret = icc_enable(pcie->icc_cpu); in qcom_pcie_resume_noirq()
1804 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_resume_noirq()
1809 if (pcie->suspended) { in qcom_pcie_resume_noirq()
1810 ret = qcom_pcie_host_init(&pcie->pci->pp); in qcom_pcie_resume_noirq()
1814 pcie->suspended = false; in qcom_pcie_resume_noirq()
1817 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_resume_noirq()
1823 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1824 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1825 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1826 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1827 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1828 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1829 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1830 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1831 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1832 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1833 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
1834 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
1835 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1836 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1837 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
1838 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1839 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1840 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1841 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1842 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1843 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1844 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1845 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1846 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
1869 .name = "qcom-pcie",