Lines Matching +full:gpio +full:- +full:ctrl2
1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/gpio/consumer.h>
24 #include "pcie-designware.h"
46 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
60 pci->app_clks[i].id = dw_pcie_app_clks[i]; in dw_pcie_get_clocks()
63 pci->core_clks[i].id = dw_pcie_core_clks[i]; in dw_pcie_get_clocks()
65 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, in dw_pcie_get_clocks()
66 pci->app_clks); in dw_pcie_get_clocks()
70 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, in dw_pcie_get_clocks()
71 pci->core_clks); in dw_pcie_get_clocks()
79 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; in dw_pcie_get_resets()
82 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; in dw_pcie_get_resets()
84 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, in dw_pcie_get_resets()
86 pci->app_rsts); in dw_pcie_get_resets()
90 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, in dw_pcie_get_resets()
92 pci->core_rsts); in dw_pcie_get_resets()
96 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); in dw_pcie_get_resets()
97 if (IS_ERR(pci->pe_rst)) in dw_pcie_get_resets()
98 return PTR_ERR(pci->pe_rst); in dw_pcie_get_resets()
105 struct platform_device *pdev = to_platform_device(pci->dev); in dw_pcie_get_resources()
106 struct device_node *np = dev_of_node(pci->dev); in dw_pcie_get_resources()
110 if (!pci->dbi_base) { in dw_pcie_get_resources()
112 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); in dw_pcie_get_resources()
113 if (IS_ERR(pci->dbi_base)) in dw_pcie_get_resources()
114 return PTR_ERR(pci->dbi_base); in dw_pcie_get_resources()
115 pci->dbi_phys_addr = res->start; in dw_pcie_get_resources()
119 if (!pci->dbi_base2) { in dw_pcie_get_resources()
122 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); in dw_pcie_get_resources()
123 if (IS_ERR(pci->dbi_base2)) in dw_pcie_get_resources()
124 return PTR_ERR(pci->dbi_base2); in dw_pcie_get_resources()
126 pci->dbi_base2 = pci->dbi_base + SZ_4K; in dw_pcie_get_resources()
130 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ in dw_pcie_get_resources()
131 if (!pci->atu_base) { in dw_pcie_get_resources()
134 pci->atu_size = resource_size(res); in dw_pcie_get_resources()
135 pci->atu_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
136 if (IS_ERR(pci->atu_base)) in dw_pcie_get_resources()
137 return PTR_ERR(pci->atu_base); in dw_pcie_get_resources()
138 pci->atu_phys_addr = res->start; in dw_pcie_get_resources()
140 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_get_resources()
145 if (!pci->atu_size) in dw_pcie_get_resources()
146 pci->atu_size = SZ_4K; in dw_pcie_get_resources()
149 if (!pci->edma.reg_base) { in dw_pcie_get_resources()
152 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
153 if (IS_ERR(pci->edma.reg_base)) in dw_pcie_get_resources()
154 return PTR_ERR(pci->edma.reg_base); in dw_pcie_get_resources()
155 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { in dw_pcie_get_resources()
156 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; in dw_pcie_get_resources()
171 if (pci->max_link_speed < 1) in dw_pcie_get_resources()
172 pci->max_link_speed = of_pci_get_max_link_speed(np); in dw_pcie_get_resources()
174 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_get_resources()
176 if (of_property_read_bool(np, "snps,enable-cdm-check")) in dw_pcie_get_resources()
191 if (pci->version && pci->version != ver) in dw_pcie_version_detect()
192 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", in dw_pcie_version_detect()
193 pci->version, ver); in dw_pcie_version_detect()
195 pci->version = ver; in dw_pcie_version_detect()
199 if (pci->type && pci->type != ver) in dw_pcie_version_detect()
200 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", in dw_pcie_version_detect()
201 pci->type, ver); in dw_pcie_version_detect()
203 pci->type = ver; in dw_pcie_version_detect()
253 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in dw_pcie_find_next_ext_capability()
266 while (ttl-- > 0) { in dw_pcie_find_next_ext_capability()
331 if (pci->ops && pci->ops->read_dbi) in dw_pcie_read_dbi()
332 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
334 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
336 dev_err(pci->dev, "Read DBI address failed\n"); in dw_pcie_read_dbi()
346 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_write_dbi()
347 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
351 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
353 dev_err(pci->dev, "Write DBI address failed\n"); in dw_pcie_write_dbi()
361 if (pci->ops && pci->ops->write_dbi2) { in dw_pcie_write_dbi2()
362 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); in dw_pcie_write_dbi2()
366 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); in dw_pcie_write_dbi2()
368 dev_err(pci->dev, "write DBI address failed\n"); in dw_pcie_write_dbi2()
376 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); in dw_pcie_select_atu()
379 return pci->atu_base; in dw_pcie_select_atu()
390 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_atu()
391 return pci->ops->read_dbi(pci, base, reg, 4); in dw_pcie_readl_atu()
395 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
408 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_writel_atu()
409 pci->ops->write_dbi(pci, base, reg, 4, val); in dw_pcie_writel_atu()
415 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
433 * bit in the Control register-1 of the ATU outbound region acts in dw_pcie_enable_ecrc()
452 * on Root Port:- TLP Digest (DWord size) gets appended to each packet in dw_pcie_enable_ecrc()
457 * on End Point:- TLP Digest is received for some/all the packets coming in dw_pcie_enable_ecrc()
473 u64 cpu_addr = atu->cpu_addr; in dw_pcie_prog_outbound_atu()
477 if (pci->ops && pci->ops->cpu_addr_fixup) in dw_pcie_prog_outbound_atu()
478 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); in dw_pcie_prog_outbound_atu()
480 limit_addr = cpu_addr + atu->size - 1; in dw_pcie_prog_outbound_atu()
482 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || in dw_pcie_prog_outbound_atu()
483 !IS_ALIGNED(cpu_addr, pci->region_align) || in dw_pcie_prog_outbound_atu()
484 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { in dw_pcie_prog_outbound_atu()
485 return -EINVAL; in dw_pcie_prog_outbound_atu()
488 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, in dw_pcie_prog_outbound_atu()
490 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, in dw_pcie_prog_outbound_atu()
493 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, in dw_pcie_prog_outbound_atu()
496 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, in dw_pcie_prog_outbound_atu()
499 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, in dw_pcie_prog_outbound_atu()
500 lower_32_bits(atu->pci_addr)); in dw_pcie_prog_outbound_atu()
501 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, in dw_pcie_prog_outbound_atu()
502 upper_32_bits(atu->pci_addr)); in dw_pcie_prog_outbound_atu()
504 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); in dw_pcie_prog_outbound_atu()
510 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); in dw_pcie_prog_outbound_atu()
513 if (atu->type == PCIE_ATU_TYPE_MSG) { in dw_pcie_prog_outbound_atu()
514 /* The data-less messages only for now */ in dw_pcie_prog_outbound_atu()
515 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; in dw_pcie_prog_outbound_atu()
517 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); in dw_pcie_prog_outbound_atu()
524 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); in dw_pcie_prog_outbound_atu()
531 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu()
533 return -ETIMEDOUT; in dw_pcie_prog_outbound_atu()
550 u64 limit_addr = pci_addr + size - 1; in dw_pcie_prog_inbound_atu()
553 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || in dw_pcie_prog_inbound_atu()
554 !IS_ALIGNED(cpu_addr, pci->region_align) || in dw_pcie_prog_inbound_atu()
555 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { in dw_pcie_prog_inbound_atu()
556 return -EINVAL; in dw_pcie_prog_inbound_atu()
594 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
596 return -ETIMEDOUT; in dw_pcie_prog_inbound_atu()
604 if (!IS_ALIGNED(cpu_addr, pci->region_align)) in dw_pcie_prog_ep_inbound_atu()
605 return -EINVAL; in dw_pcie_prog_ep_inbound_atu()
630 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_ep_inbound_atu()
632 return -ETIMEDOUT; in dw_pcie_prog_ep_inbound_atu()
654 dev_info(pci->dev, "Phy link never came up\n"); in dw_pcie_wait_for_link()
655 return -ETIMEDOUT; in dw_pcie_wait_for_link()
661 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", in dw_pcie_wait_for_link()
673 if (pci->ops && pci->ops->link_up) in dw_pcie_link_up()
674 return pci->ops->link_up(pci); in dw_pcie_link_up()
694 u32 cap, ctrl2, link_speed; in dw_pcie_link_set_max_speed() local
704 if (pci->max_link_speed < 1) { in dw_pcie_link_set_max_speed()
705 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); in dw_pcie_link_set_max_speed()
709 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); in dw_pcie_link_set_max_speed()
710 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; in dw_pcie_link_set_max_speed()
712 switch (pcie_link_speed[pci->max_link_speed]) { in dw_pcie_link_set_max_speed()
728 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; in dw_pcie_link_set_max_speed()
732 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); in dw_pcie_link_set_max_speed()
773 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); in dw_pcie_link_set_max_link_width()
796 max_region = min((int)pci->atu_size / 512, 256); in dw_pcie_iatu_detect()
798 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; in dw_pcie_iatu_detect()
799 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; in dw_pcie_iatu_detect()
824 dev_err(pci->dev, "No iATU regions found\n"); in dw_pcie_iatu_detect()
838 pci->num_ob_windows = ob; in dw_pcie_iatu_detect()
839 pci->num_ib_windows = ib; in dw_pcie_iatu_detect()
840 pci->region_align = 1 << fls(min); in dw_pcie_iatu_detect()
841 pci->region_limit = (max << 32) | (SZ_4G - 1); in dw_pcie_iatu_detect()
843 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", in dw_pcie_iatu_detect()
845 pci->num_ob_windows, pci->num_ib_windows, in dw_pcie_iatu_detect()
846 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); in dw_pcie_iatu_detect()
854 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_dma()
855 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); in dw_pcie_readl_dma()
857 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); in dw_pcie_readl_dma()
859 dev_err(pci->dev, "Read DMA address failed\n"); in dw_pcie_readl_dma()
871 return -EINVAL; in dw_pcie_edma_irq_vector()
888 pci->edma.dev = pci->dev; in dw_pcie_edma_init_data()
890 if (!pci->edma.ops) in dw_pcie_edma_init_data()
891 pci->edma.ops = &dw_pcie_edma_ops; in dw_pcie_edma_init_data()
893 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; in dw_pcie_edma_init_data()
905 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) in dw_pcie_edma_find_mf()
906 return pci->edma.reg_base ? 0 : -ENODEV; in dw_pcie_edma_find_mf()
918 if (val == 0xFFFFFFFF && pci->edma.reg_base) { in dw_pcie_edma_find_mf()
919 pci->edma.mf = EDMA_MF_EDMA_UNROLL; in dw_pcie_edma_find_mf()
921 pci->edma.mf = EDMA_MF_EDMA_LEGACY; in dw_pcie_edma_find_mf()
923 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; in dw_pcie_edma_find_mf()
925 return -ENODEV; in dw_pcie_edma_find_mf()
936 * Autodetect the read/write channels count only for non-HDMA platforms. in dw_pcie_edma_find_channels()
941 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { in dw_pcie_edma_find_channels()
944 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); in dw_pcie_edma_find_channels()
945 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); in dw_pcie_edma_find_channels()
949 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || in dw_pcie_edma_find_channels()
950 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) in dw_pcie_edma_find_channels()
951 return -EINVAL; in dw_pcie_edma_find_channels()
971 struct platform_device *pdev = to_platform_device(pci->dev); in dw_pcie_edma_irq_verify()
972 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; in dw_pcie_edma_irq_verify()
976 if (pci->edma.nr_irqs == 1) in dw_pcie_edma_irq_verify()
978 else if (pci->edma.nr_irqs > 1) in dw_pcie_edma_irq_verify()
979 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; in dw_pcie_edma_irq_verify()
983 pci->edma.nr_irqs = 1; in dw_pcie_edma_irq_verify()
987 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { in dw_pcie_edma_irq_verify()
988 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); in dw_pcie_edma_irq_verify()
992 return -EINVAL; in dw_pcie_edma_irq_verify()
1004 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { in dw_pcie_edma_ll_alloc()
1005 ll = &pci->edma.ll_region_wr[i]; in dw_pcie_edma_ll_alloc()
1006 ll->sz = DMA_LLP_MEM_SIZE; in dw_pcie_edma_ll_alloc()
1007 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, in dw_pcie_edma_ll_alloc()
1009 if (!ll->vaddr.mem) in dw_pcie_edma_ll_alloc()
1010 return -ENOMEM; in dw_pcie_edma_ll_alloc()
1012 ll->paddr = paddr; in dw_pcie_edma_ll_alloc()
1015 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { in dw_pcie_edma_ll_alloc()
1016 ll = &pci->edma.ll_region_rd[i]; in dw_pcie_edma_ll_alloc()
1017 ll->sz = DMA_LLP_MEM_SIZE; in dw_pcie_edma_ll_alloc()
1018 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, in dw_pcie_edma_ll_alloc()
1020 if (!ll->vaddr.mem) in dw_pcie_edma_ll_alloc()
1021 return -ENOMEM; in dw_pcie_edma_ll_alloc()
1023 ll->paddr = paddr; in dw_pcie_edma_ll_alloc()
1041 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); in dw_pcie_edma_detect()
1047 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); in dw_pcie_edma_detect()
1052 ret = dw_edma_probe(&pci->edma); in dw_pcie_edma_detect()
1053 if (ret && ret != -ENODEV) { in dw_pcie_edma_detect()
1054 dev_err(pci->dev, "Couldn't register eDMA device\n"); in dw_pcie_edma_detect()
1058 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", in dw_pcie_edma_detect()
1059 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", in dw_pcie_edma_detect()
1060 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); in dw_pcie_edma_detect()
1067 dw_edma_remove(&pci->edma); in dw_pcie_edma_remove()
1077 if (pci->n_fts[0]) { in dw_pcie_setup()
1080 val |= PORT_AFR_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
1081 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
1086 if (pci->n_fts[1]) { in dw_pcie_setup()
1089 val |= pci->n_fts[1]; in dw_pcie_setup()
1105 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); in dw_pcie_setup()