Lines Matching +full:syscon +full:- +full:pcie +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Texas Instruments Keystone SoCs
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
19 #include <linux/mfd/syscon.h>
31 #include "pcie-designware.h"
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
90 /* PCIE controller device IDs */
97 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) argument
110 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
115 enum dw_pcie_device_mode mode; member
144 return readl(ks_pcie->va_app_base + offset); in ks_pcie_app_readl()
150 writel(val, ks_pcie->va_app_base + offset); in ks_pcie_app_writel()
157 u32 irq = data->hwirq; in ks_pcie_msi_irq_ack()
183 msi_target = ks_pcie->app.start + MSI_IRQ; in ks_pcie_compose_msi_msg()
184 msg->address_lo = lower_32_bits(msi_target); in ks_pcie_compose_msi_msg()
185 msg->address_hi = upper_32_bits(msi_target); in ks_pcie_compose_msi_msg()
186 msg->data = data->hwirq; in ks_pcie_compose_msi_msg()
188 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", in ks_pcie_compose_msi_msg()
189 (int)data->hwirq, msg->address_hi, msg->address_lo); in ks_pcie_compose_msi_msg()
196 u32 irq = data->hwirq; in ks_pcie_msi_mask()
202 raw_spin_lock_irqsave(&pp->lock, flags); in ks_pcie_msi_mask()
213 raw_spin_unlock_irqrestore(&pp->lock, flags); in ks_pcie_msi_mask()
220 u32 irq = data->hwirq; in ks_pcie_msi_unmask()
226 raw_spin_lock_irqsave(&pp->lock, flags); in ks_pcie_msi_unmask()
237 raw_spin_unlock_irqrestore(&pp->lock, flags); in ks_pcie_msi_unmask()
241 .name = "KEYSTONE-PCI-MSI",
249 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
251 * PCIe host controller driver information.
270 * ks_pcie_clear_dbi_mode() - Disable DBI mode
272 * PCIe host controller driver information.
300 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); in ks_pcie_msi_host_init()
308 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); in ks_pcie_msi_host_init()
310 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; in ks_pcie_msi_host_init()
317 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_handle_intx_irq()
318 struct device *dev = pci->dev; in ks_pcie_handle_intx_irq()
325 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset); in ks_pcie_handle_intx_irq()
340 struct device *dev = ks_pcie->pci->dev; in ks_pcie_handle_error_irq()
358 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) in ks_pcie_handle_error_irq()
361 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) in ks_pcie_handle_error_irq()
382 .name = "Keystone-PCI-INTX-IRQ",
393 irq_set_chip_data(irq, d->host_data); in ks_pcie_init_intx_irq_map()
406 u32 num_viewport = ks_pcie->num_viewport; in ks_pcie_setup_rc_app_regs()
407 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_setup_rc_app_regs()
408 struct dw_pcie_rp *pp = &pci->pp; in ks_pcie_setup_rc_app_regs()
414 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); in ks_pcie_setup_rc_app_regs()
416 return -ENODEV; in ks_pcie_setup_rc_app_regs()
418 mem = entry->res; in ks_pcie_setup_rc_app_regs()
419 start = mem->start; in ks_pcie_setup_rc_app_regs()
420 end = mem->end; in ks_pcie_setup_rc_app_regs()
428 if (ks_pcie->is_am6) in ks_pcie_setup_rc_app_regs()
434 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ in ks_pcie_setup_rc_app_regs()
453 struct dw_pcie_rp *pp = bus->sysdata; in ks_pcie_other_map_bus()
458 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | in ks_pcie_other_map_bus()
460 if (!pci_is_root_bus(bus->parent)) in ks_pcie_other_map_bus()
464 return pp->va_cfg0_base + where; in ks_pcie_other_map_bus()
480 * ks_pcie_link_up() - Check if link up
481 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host
518 struct pci_bus *bus = dev->bus; in ks_pcie_quirk()
546 bridge = bus->self; in ks_pcie_quirk()
547 bus = bus->parent; in ks_pcie_quirk()
561 dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); in ks_pcie_quirk()
573 if (!bridge_dev || !bridge_dev->parent) in ks_pcie_quirk()
576 ks_pcie = dev_get_drvdata(bridge_dev->parent); in ks_pcie_quirk()
587 dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); in ks_pcie_quirk()
596 unsigned int irq = desc->irq_data.hwirq; in ks_pcie_msi_irq_handler()
598 u32 offset = irq - ks_pcie->msi_host_irq; in ks_pcie_msi_irq_handler()
599 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_msi_irq_handler()
600 struct dw_pcie_rp *pp = &pci->pp; in ks_pcie_msi_irq_handler()
601 struct device *dev = pci->dev; in ks_pcie_msi_irq_handler()
616 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit in ks_pcie_msi_irq_handler()
625 generic_handle_domain_irq(pp->irq_domain, vector); in ks_pcie_msi_irq_handler()
632 * ks_pcie_intx_irq_handler() - Handle INTX interrupt
642 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_intx_irq_handler()
643 struct device *dev = pci->dev; in ks_pcie_intx_irq_handler()
644 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0]; in ks_pcie_intx_irq_handler()
661 struct device *dev = ks_pcie->pci->dev; in ks_pcie_config_msi_irq()
662 struct device_node *np = ks_pcie->np; in ks_pcie_config_msi_irq()
670 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); in ks_pcie_config_msi_irq()
672 if (ks_pcie->is_am6) in ks_pcie_config_msi_irq()
674 dev_warn(dev, "msi-interrupt-controller node is absent\n"); in ks_pcie_config_msi_irq()
675 return -EINVAL; in ks_pcie_config_msi_irq()
680 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); in ks_pcie_config_msi_irq()
681 ret = -EINVAL; in ks_pcie_config_msi_irq()
688 ret = -EINVAL; in ks_pcie_config_msi_irq()
692 if (!ks_pcie->msi_host_irq) { in ks_pcie_config_msi_irq()
695 ret = -EINVAL; in ks_pcie_config_msi_irq()
698 ks_pcie->msi_host_irq = irq_data->hwirq; in ks_pcie_config_msi_irq()
715 struct device *dev = ks_pcie->pci->dev; in ks_pcie_config_intx_irq()
717 struct device_node *np = ks_pcie->np; in ks_pcie_config_intx_irq()
721 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); in ks_pcie_config_intx_irq()
724 * Since INTX interrupts are modeled as edge-interrupts in in ks_pcie_config_intx_irq()
727 if (ks_pcie->is_am6) in ks_pcie_config_intx_irq()
729 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); in ks_pcie_config_intx_irq()
730 return -EINVAL; in ks_pcie_config_intx_irq()
735 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); in ks_pcie_config_intx_irq()
736 ret = -EINVAL; in ks_pcie_config_intx_irq()
743 ret = -EINVAL; in ks_pcie_config_intx_irq()
746 ks_pcie->intx_host_irqs[i] = irq; in ks_pcie_config_intx_irq()
757 ret = -EINVAL; in ks_pcie_config_intx_irq()
760 ks_pcie->intx_irq_domain = intx_irq_domain; in ks_pcie_config_intx_irq()
784 regs->uregs[reg] = -1; in ks_pcie_fault()
785 regs->ARM_pc += 4; in ks_pcie_fault()
797 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_init_id()
798 struct device *dev = pci->dev; in ks_pcie_init_id()
799 struct device_node *np = dev->of_node; in ks_pcie_init_id()
803 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); in ks_pcie_init_id()
808 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); in ks_pcie_init_id()
830 pp->bridge->ops = &ks_pcie_ops; in ks_pcie_host_init()
831 if (!ks_pcie->is_am6) in ks_pcie_host_init()
832 pp->bridge->child_ops = &ks_child_pcie_ops; in ks_pcie_host_init()
848 pci->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
856 * PCIe access errors that result into OCP errors are caught by ARM as in ks_pcie_host_init()
904 ep->page_size = AM654_WIN_SIZE; in ks_pcie_am654_ep_init()
906 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); in ks_pcie_am654_ep_init()
912 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_am654_raise_intx_irq()
945 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in ks_pcie_am654_raise_irq()
946 return -EINVAL; in ks_pcie_am654_raise_irq()
979 int num_lanes = ks_pcie->num_lanes; in ks_pcie_disable_phy()
981 while (num_lanes--) { in ks_pcie_disable_phy()
982 phy_power_off(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
983 phy_exit(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
991 int num_lanes = ks_pcie->num_lanes; in ks_pcie_enable_phy()
994 ret = phy_reset(ks_pcie->phy[i]); in ks_pcie_enable_phy()
998 ret = phy_init(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1002 ret = phy_power_on(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1004 phy_exit(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1012 while (--i >= 0) { in ks_pcie_enable_phy()
1013 phy_power_off(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1014 phy_exit(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1022 struct device_node *np = dev->of_node; in ks_pcie_set_mode()
1025 struct regmap *syscon; in ks_pcie_set_mode() local
1030 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); in ks_pcie_set_mode()
1031 if (IS_ERR(syscon)) in ks_pcie_set_mode()
1035 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); in ks_pcie_set_mode()
1042 ret = regmap_update_bits(syscon, offset, mask, val); in ks_pcie_set_mode()
1044 dev_err(dev, "failed to set pcie mode\n"); in ks_pcie_set_mode()
1052 enum dw_pcie_device_mode mode) in ks_pcie_am654_set_mode() argument
1054 struct device_node *np = dev->of_node; in ks_pcie_am654_set_mode()
1057 struct regmap *syscon; in ks_pcie_am654_set_mode() local
1062 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); in ks_pcie_am654_set_mode()
1063 if (IS_ERR(syscon)) in ks_pcie_am654_set_mode()
1067 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); in ks_pcie_am654_set_mode()
1073 switch (mode) { in ks_pcie_am654_set_mode()
1081 dev_err(dev, "INVALID device type %d\n", mode); in ks_pcie_am654_set_mode()
1082 return -EINVAL; in ks_pcie_am654_set_mode()
1085 ret = regmap_update_bits(syscon, offset, mask, val); in ks_pcie_am654_set_mode()
1087 dev_err(dev, "failed to set pcie mode\n"); in ks_pcie_am654_set_mode()
1101 .mode = DW_PCIE_RC_TYPE,
1107 .mode = DW_PCIE_EP_TYPE,
1115 .compatible = "ti,keystone-pcie",
1119 .compatible = "ti,am654-pcie-rc",
1123 .compatible = "ti,am654-pcie-ep",
1132 struct device *dev = &pdev->dev; in ks_pcie_probe()
1133 struct device_node *np = dev->of_node; in ks_pcie_probe()
1135 enum dw_pcie_device_mode mode; in ks_pcie_probe() local
1153 return -EINVAL; in ks_pcie_probe()
1155 version = data->version; in ks_pcie_probe()
1156 host_ops = data->host_ops; in ks_pcie_probe()
1157 ep_ops = data->ep_ops; in ks_pcie_probe()
1158 mode = data->mode; in ks_pcie_probe()
1162 return -ENOMEM; in ks_pcie_probe()
1166 return -ENOMEM; in ks_pcie_probe()
1169 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); in ks_pcie_probe()
1170 if (IS_ERR(ks_pcie->va_app_base)) in ks_pcie_probe()
1171 return PTR_ERR(ks_pcie->va_app_base); in ks_pcie_probe()
1173 ks_pcie->app = *res; in ks_pcie_probe()
1180 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) in ks_pcie_probe()
1181 ks_pcie->is_am6 = true; in ks_pcie_probe()
1183 pci->dbi_base = base; in ks_pcie_probe()
1184 pci->dbi_base2 = base; in ks_pcie_probe()
1185 pci->dev = dev; in ks_pcie_probe()
1186 pci->ops = &ks_pcie_dw_pcie_ops; in ks_pcie_probe()
1187 pci->version = version; in ks_pcie_probe()
1194 "ks-pcie-error-irq", ks_pcie); in ks_pcie_probe()
1201 ret = of_property_read_u32(np, "num-lanes", &num_lanes); in ks_pcie_probe()
1207 return -ENOMEM; in ks_pcie_probe()
1211 return -ENOMEM; in ks_pcie_probe()
1214 snprintf(name, sizeof(name), "pcie-phy%d", i); in ks_pcie_probe()
1224 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); in ks_pcie_probe()
1226 ret = -EINVAL; in ks_pcie_probe()
1231 ks_pcie->np = np; in ks_pcie_probe()
1232 ks_pcie->pci = pci; in ks_pcie_probe()
1233 ks_pcie->link = link; in ks_pcie_probe()
1234 ks_pcie->num_lanes = num_lanes; in ks_pcie_probe()
1235 ks_pcie->phy = phy; in ks_pcie_probe()
1241 if (ret != -EPROBE_DEFER) in ks_pcie_probe()
1248 phy_pm_runtime_get_sync(ks_pcie->phy[i]); in ks_pcie_probe()
1254 phy_pm_runtime_put_sync(ks_pcie->phy[i]); in ks_pcie_probe()
1270 ret = ks_pcie_am654_set_mode(dev, mode); in ks_pcie_probe()
1276 switch (mode) { in ks_pcie_probe()
1279 ret = -ENODEV; in ks_pcie_probe()
1283 ret = of_property_read_u32(np, "num-viewport", &num_viewport); in ks_pcie_probe()
1285 dev_err(dev, "unable to read *num-viewport* property\n"); in ks_pcie_probe()
1294 * mode is selected while enabling the PHY. So deassert PERST# in ks_pcie_probe()
1302 ks_pcie->num_viewport = num_viewport; in ks_pcie_probe()
1303 pci->pp.ops = host_ops; in ks_pcie_probe()
1304 ret = dw_pcie_host_init(&pci->pp); in ks_pcie_probe()
1310 ret = -ENODEV; in ks_pcie_probe()
1314 pci->ep.ops = ep_ops; in ks_pcie_probe()
1315 ret = dw_pcie_ep_init(&pci->ep); in ks_pcie_probe()
1319 ret = dw_pcie_ep_init_registers(&pci->ep); in ks_pcie_probe()
1325 pci_epc_init_notify(pci->ep.epc); in ks_pcie_probe()
1329 dev_err(dev, "INVALID device type %d\n", mode); in ks_pcie_probe()
1337 dw_pcie_ep_deinit(&pci->ep); in ks_pcie_probe()
1344 while (--i >= 0 && link[i]) in ks_pcie_probe()
1353 struct device_link **link = ks_pcie->link; in ks_pcie_remove()
1354 int num_lanes = ks_pcie->num_lanes; in ks_pcie_remove()
1355 struct device *dev = &pdev->dev; in ks_pcie_remove()
1360 while (num_lanes--) in ks_pcie_remove()
1368 .name = "keystone-pcie",