Lines Matching +full:pcie +full:- +full:6
1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
79 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
81 (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
105 (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6))
107 (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6))
109 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))
111 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))
113 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6))
115 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6))
117 (((aperture) - 2) << ((bar) * 8))
150 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
155 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
163 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
167 /* Region r Outbound PCIe Descriptor Register 0 */
183 /* Region r Outbound PCIe Descriptor Register 1 */
195 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
201 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
206 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
222 RP_BAR_UNDEFINED = -1,
236 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
285 int (*start_link)(struct cdns_pcie *pcie);
286 void (*stop_link)(struct cdns_pcie *pcie);
287 bool (*link_up)(struct cdns_pcie *pcie);
288 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
292 * struct cdns_pcie - private data for Cadence PCIe controller drivers
295 * @dev: PCIe controller
296 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
300 * @ops: Platform-specific ops to control various inputs from Cadence PCIe
315 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
316 * @pcie: Cadence PCIe controller
325 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
329 struct cdns_pcie pcie; member
340 * struct cdns_pcie_epf - Structure to hold info about endpoint function
350 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
351 * @pcie: Cadence PCIe controller
359 * IRQ) TLP through the PCIe bus.
365 * @lock: spin lock to disable interrupts while modifying PCIe controller
373 struct cdns_pcie pcie; member
391 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) in cdns_pcie_writel() argument
393 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
396 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) in cdns_pcie_readl() argument
398 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
415 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); in cdns_pcie_read_sz()
435 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); in cdns_pcie_write_sz()
442 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, in cdns_pcie_rp_writeb() argument
445 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writeb()
450 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, in cdns_pcie_rp_writew() argument
453 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writew()
458 static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) in cdns_pcie_rp_readw() argument
460 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_readw()
466 static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writeb() argument
469 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writeb()
474 static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writew() argument
477 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writew()
482 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writel() argument
485 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writel()
488 static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) in cdns_pcie_ep_fn_readw() argument
490 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_readw()
495 static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) in cdns_pcie_ep_fn_readl() argument
497 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_readl()
500 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) in cdns_pcie_start_link() argument
502 if (pcie->ops->start_link) in cdns_pcie_start_link()
503 return pcie->ops->start_link(pcie); in cdns_pcie_start_link()
508 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) in cdns_pcie_stop_link() argument
510 if (pcie->ops->stop_link) in cdns_pcie_stop_link()
511 pcie->ops->stop_link(pcie); in cdns_pcie_stop_link()
514 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) in cdns_pcie_link_up() argument
516 if (pcie->ops->link_up) in cdns_pcie_link_up()
517 return pcie->ops->link_up(pcie); in cdns_pcie_link_up()
560 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
562 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
566 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
570 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
571 void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
572 int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
573 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);