Lines Matching +full:ati +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 ** (c) Copyright 1999,2000 Hewlett-Packard Company
12 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
13 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
20 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
27 ** FIXME: Add support for PCI card hot-plug (OLARD).
46 #include <asm/parisc-device.h>
54 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
56 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
85 ** Config accessor functions only pass in the 8-bit bus number and not
86 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
100 /* non-postable I/O port space, densely packed */
109 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
155 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
166 printk(KERN_DEBUG "(%p)", r->parent); in lba_dump_res()
167 for (i = d; i ; --i) printk(" "); in lba_dump_res()
169 (long)r->start, (long)r->end, r->flags); in lba_dump_res()
170 lba_dump_res(r->child, d+2); in lba_dump_res()
171 lba_dump_res(r->sibling, d); in lba_dump_res()
178 ** -- preserve LBA state
179 ** -- prevent any DMA from occurring
180 ** -- turn on smart mode
181 ** -- probe with config writes before doing config reads
182 ** -- check ERROR_STATUS
183 ** -- clear ERROR_STATUS
184 ** -- restore LBA state
191 u8 first_bus = d->hba.hba_bus->busn_res.start; in lba_device_present()
192 u8 last_sub_bus = d->hba.hba_bus->busn_res.end; in lba_device_present()
196 ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) { in lba_device_present()
207 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
216 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
222 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
228 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
237 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
242 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
245 * Vendor ID register since read-only). \
247 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
252 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
258 * -- Can't tell if config cycle got the error.
265 * -- Even if we could tell, we still want to return -1
268 * -- Only clear non-fatal errors (we don't want to bring
269 * LBA out of pci-fatal mode).
283 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \ argument
287 * errors are logged -- LBA HW ERS section 14.3.3). \
289 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
290 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
301 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
307 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
310 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
315 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
319 #define LBA_CFG_RESTORE(d, base) { \ argument
323 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
327 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
331 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
347 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); in lba_rd_cfg()
349 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in lba_rd_cfg()
358 LBA_CFG_RESTORE(d, d->hba.base_addr); in lba_rd_cfg()
365 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); in elroy_cfg_read()
366 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; in elroy_cfg_read()
368 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in elroy_cfg_read()
371 return -EINVAL; in elroy_cfg_read()
375 /* original - Generate config cycle on broken elroy in elroy_cfg_read()
378 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data); in elroy_cfg_read()
382 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) { in elroy_cfg_read()
383 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos); in elroy_cfg_read()
399 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data); in elroy_cfg_read()
411 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in lba_wr_cfg()
420 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); in lba_wr_cfg()
421 LBA_CFG_RESTORE(d, d->hba.base_addr); in lba_wr_cfg()
426 * LBA 4.0 config write code implements non-postable semantics
432 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); in elroy_cfg_write()
433 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; in elroy_cfg_write()
437 return -EINVAL; in elroy_cfg_write()
446 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) { in elroy_cfg_write()
456 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); in elroy_cfg_write()
458 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); in elroy_cfg_write()
460 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); in elroy_cfg_write()
464 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); in elroy_cfg_write()
482 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); in mercury_cfg_read()
483 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; in mercury_cfg_read()
485 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in mercury_cfg_read()
488 return -EINVAL; in mercury_cfg_read()
503 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data); in mercury_cfg_read()
508 * LBA 4.0 config write code implements non-postable semantics
514 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); in mercury_cfg_write()
515 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in mercury_cfg_write()
516 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; in mercury_cfg_write()
520 return -EINVAL; in mercury_cfg_write()
522 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data); in mercury_cfg_write()
538 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); in mercury_cfg_write()
573 unsigned long start = new->start; in truncate_pat_collision()
574 unsigned long end = new->end; in truncate_pat_collision()
575 struct resource *tmp = root->child; in truncate_pat_collision()
577 if (end <= start || start < root->start || !tmp) in truncate_pat_collision()
581 while (tmp && tmp->end < start) in truncate_pat_collision()
582 tmp = tmp->sibling; in truncate_pat_collision()
590 if (tmp->start >= end) return 0; in truncate_pat_collision()
592 if (tmp->start <= start) { in truncate_pat_collision()
594 new->start = tmp->end + 1; in truncate_pat_collision()
596 if (tmp->end >= end) { in truncate_pat_collision()
602 if (tmp->end < end ) { in truncate_pat_collision()
604 new->end = tmp->start - 1; in truncate_pat_collision()
610 (long)new->start, (long)new->end ); in truncate_pat_collision()
618 * This is needed at least on C8000 systems to get the ATI FireGL card
631 end - start, lba_len); in extend_lmmio_len()
635 pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end); in extend_lmmio_len()
640 end = -1ULL; in extend_lmmio_len()
642 pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end); in extend_lmmio_len()
645 for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) { in extend_lmmio_len()
647 if (tmp->start == start) in extend_lmmio_len()
649 if (tmp->end < start) in extend_lmmio_len()
651 if (tmp->start > end) in extend_lmmio_len()
653 if (end >= tmp->start) in extend_lmmio_len()
654 end = tmp->start - 1; in extend_lmmio_len()
657 pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end); in extend_lmmio_len()
673 r = &dev->resource[idx]; in pcibios_allocate_bridge_resources()
674 if (!r->flags) in pcibios_allocate_bridge_resources()
676 if (r->parent) /* Already allocated */ in pcibios_allocate_bridge_resources()
678 if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) { in pcibios_allocate_bridge_resources()
685 r->start = r->end = 0; in pcibios_allocate_bridge_resources()
686 r->flags = 0; in pcibios_allocate_bridge_resources()
695 /* Depth-First Search on bus tree */ in pcibios_allocate_bus_resources()
696 if (bus->self) in pcibios_allocate_bus_resources()
697 pcibios_allocate_bridge_resources(bus->self); in pcibios_allocate_bus_resources()
698 list_for_each_entry(child, &bus->children, node) in pcibios_allocate_bus_resources()
705 ** But it needs to access local data structures to get the IRQ base.
719 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge)); in lba_fixup_bus()
722 bus, (int)bus->busn_res.start, bus->bridge->platform_data); in lba_fixup_bus()
728 if (bus->parent) { in lba_fixup_bus()
729 /* PCI-PCI Bridge */ in lba_fixup_bus()
735 /* Host-PCI Bridge */ in lba_fixup_bus()
739 ldev->hba.io_space.name, in lba_fixup_bus()
740 ldev->hba.io_space.start, ldev->hba.io_space.end, in lba_fixup_bus()
741 ldev->hba.io_space.flags); in lba_fixup_bus()
743 ldev->hba.lmmio_space.name, in lba_fixup_bus()
744 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, in lba_fixup_bus()
745 ldev->hba.lmmio_space.flags); in lba_fixup_bus()
747 err = request_resource(&ioport_resource, &(ldev->hba.io_space)); in lba_fixup_bus()
753 if (ldev->hba.elmmio_space.flags) { in lba_fixup_bus()
755 &(ldev->hba.elmmio_space)); in lba_fixup_bus()
760 (long)ldev->hba.elmmio_space.start, in lba_fixup_bus()
761 (long)ldev->hba.elmmio_space.end); in lba_fixup_bus()
768 if (ldev->hba.lmmio_space.flags) { in lba_fixup_bus()
769 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); in lba_fixup_bus()
773 (long)ldev->hba.lmmio_space.start, in lba_fixup_bus()
774 (long)ldev->hba.lmmio_space.end); in lba_fixup_bus()
780 if (ldev->hba.gmmio_space.flags) { in lba_fixup_bus()
781 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); in lba_fixup_bus()
785 (long)ldev->hba.gmmio_space.start, in lba_fixup_bus()
786 (long)ldev->hba.gmmio_space.end); in lba_fixup_bus()
795 list_for_each_entry(dev, &bus->devices, bus_list) { in lba_fixup_bus()
802 struct resource *res = &dev->resource[i]; in lba_fixup_bus()
804 /* If resource not allocated - skip it */ in lba_fixup_bus()
805 if (!res->start) in lba_fixup_bus()
822 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK); in lba_fixup_bus()
828 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in lba_fixup_bus()
834 iosapic_fixup_irq(ldev->iosapic_obj, dev); in lba_fixup_bus()
838 /* FIXME/REVISIT - finish figuring out to set FBB on both in lba_fixup_bus()
843 if (bus->parent) { in lba_fixup_bus()
846 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); in lba_fixup_bus()
847 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK); in lba_fixup_bus()
856 list_for_each_entry(dev, &bus->devices, bus_list) { in lba_fixup_bus()
903 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
906 ** guarantee non-postable completion semantics - not avoid X4107.
909 ** since we don't know what has side-effects. Attempting to read
933 if (LBA_DEV(d)->hw_rev < 3) \
934 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
954 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
966 ** Then add the base and we can generate an I/O Port cycle.
973 DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
992 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1039 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, in lba_pat_resources()
1041 pa_count = pa_pdc_cell->mod[1]; in lba_pat_resources()
1043 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, in lba_pat_resources()
1045 io_count = io_pdc_cell->mod[1]; in lba_pat_resources()
1052 if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) { in lba_pat_resources()
1067 p = (void *) &(pa_pdc_cell->mod[2+i*3]); in lba_pat_resources()
1068 io = (void *) &(io_pdc_cell->mod[2+i*3]); in lba_pat_resources()
1071 switch(p->type & 0xff) { in lba_pat_resources()
1073 lba_dev->hba.bus_num.start = p->start; in lba_pat_resources()
1074 lba_dev->hba.bus_num.end = p->end; in lba_pat_resources()
1075 lba_dev->hba.bus_num.flags = IORESOURCE_BUS; in lba_pat_resources()
1079 /* used to fix up pre-initialized MEM BARs */ in lba_pat_resources()
1080 if (!lba_dev->hba.lmmio_space.flags) { in lba_pat_resources()
1083 lba_len = ~READ_REG32(lba_dev->hba.base_addr in lba_pat_resources()
1085 if ((p->end - p->start) != lba_len) in lba_pat_resources()
1086 p->end = extend_lmmio_len(p->start, in lba_pat_resources()
1087 p->end, lba_len); in lba_pat_resources()
1089 sprintf(lba_dev->hba.lmmio_name, in lba_pat_resources()
1091 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1092 lba_dev->hba.lmmio_space_offset = p->start - in lba_pat_resources()
1093 io->start; in lba_pat_resources()
1094 r = &lba_dev->hba.lmmio_space; in lba_pat_resources()
1095 r->name = lba_dev->hba.lmmio_name; in lba_pat_resources()
1096 } else if (!lba_dev->hba.elmmio_space.flags) { in lba_pat_resources()
1097 sprintf(lba_dev->hba.elmmio_name, in lba_pat_resources()
1099 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1100 r = &lba_dev->hba.elmmio_space; in lba_pat_resources()
1101 r->name = lba_dev->hba.elmmio_name; in lba_pat_resources()
1108 r->start = p->start; in lba_pat_resources()
1109 r->end = p->end; in lba_pat_resources()
1110 r->flags = IORESOURCE_MEM; in lba_pat_resources()
1111 r->parent = r->sibling = r->child = NULL; in lba_pat_resources()
1115 /* MMIO space > 4GB phys addr; for 64-bit BAR */ in lba_pat_resources()
1116 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO", in lba_pat_resources()
1117 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1118 r = &lba_dev->hba.gmmio_space; in lba_pat_resources()
1119 r->name = lba_dev->hba.gmmio_name; in lba_pat_resources()
1120 r->start = p->start; in lba_pat_resources()
1121 r->end = p->end; in lba_pat_resources()
1122 r->flags = IORESOURCE_MEM; in lba_pat_resources()
1123 r->parent = r->sibling = r->child = NULL; in lba_pat_resources()
1129 i, p->start); in lba_pat_resources()
1135 ** base of 64MB PIOP region in lba_pat_resources()
1137 lba_dev->iop_base = ioremap(p->start, 64 * 1024 * 1024); in lba_pat_resources()
1139 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", in lba_pat_resources()
1140 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1141 r = &lba_dev->hba.io_space; in lba_pat_resources()
1142 r->name = lba_dev->hba.io_name; in lba_pat_resources()
1143 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); in lba_pat_resources()
1144 r->end = r->start + HBA_PORT_SPACE_SIZE - 1; in lba_pat_resources()
1145 r->flags = IORESOURCE_IO; in lba_pat_resources()
1146 r->parent = r->sibling = r->child = NULL; in lba_pat_resources()
1152 i, p->type & 0xff); in lba_pat_resources()
1173 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; in lba_legacy_resources()
1177 ** represents bus->secondary and the second byte represents in lba_legacy_resources()
1178 ** bus->subsidiary (i.e. highest PPB programmed by firmware). in lba_legacy_resources()
1182 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); in lba_legacy_resources()
1183 r = &(lba_dev->hba.bus_num); in lba_legacy_resources()
1184 r->name = "LBA PCI Busses"; in lba_legacy_resources()
1185 r->start = lba_num & 0xff; in lba_legacy_resources()
1186 r->end = (lba_num>>8) & 0xff; in lba_legacy_resources()
1187 r->flags = IORESOURCE_BUS; in lba_legacy_resources()
1189 /* Set up local PCI Bus resources - we don't need them for in lba_legacy_resources()
1192 r = &(lba_dev->hba.lmmio_space); in lba_legacy_resources()
1193 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO", in lba_legacy_resources()
1194 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1195 r->name = lba_dev->hba.lmmio_name; in lba_legacy_resources()
1198 /* We want the CPU -> IO routing of addresses. in lba_legacy_resources()
1199 * The SBA BASE/MASK registers control CPU -> IO routing. in lba_legacy_resources()
1205 * The LBA BASE/MASK registers control IO -> System routing. in lba_legacy_resources()
1209 * the LBA BASE/MASE registers to be the exact inverse of in lba_legacy_resources()
1214 * reprogram LBA BASE/MASK registers. Thus preserve the code in lba_legacy_resources()
1219 * f0000000-f0ffffff : PCI00 LMMIO in lba_legacy_resources()
1220 * f05d0000-f05d0000 : lcd_data in lba_legacy_resources()
1221 * f05d0008-f05d0008 : lcd_cmd in lba_legacy_resources()
1222 * f1000000-f1ffffff : PCI01 LMMIO in lba_legacy_resources()
1223 * f4000000-f4ffffff : PCI02 LMMIO in lba_legacy_resources()
1224 * f4000000-f4001fff : sym53c8xx in lba_legacy_resources()
1225 * f4002000-f4003fff : sym53c8xx in lba_legacy_resources()
1226 * f4004000-f40043ff : sym53c8xx in lba_legacy_resources()
1227 * f4005000-f40053ff : sym53c8xx in lba_legacy_resources()
1228 * f4007000-f4007fff : ohci_hcd in lba_legacy_resources()
1229 * f4008000-f40083ff : tulip in lba_legacy_resources()
1230 * f6000000-f6ffffff : PCI03 LMMIO in lba_legacy_resources()
1231 * f8000000-fbffffff : PCI00 ELMMIO in lba_legacy_resources()
1232 * fa100000-fa4fffff : stifb mmio in lba_legacy_resources()
1233 * fb000000-fb1fffff : stifb fb in lba_legacy_resources()
1246 * f4000000-f47fffff : PCI00 LMMIO in lba_legacy_resources()
1247 * f4000000-f4001fff : sym53c8xx in lba_legacy_resources()
1248 * ...[deteled core devices - same as above]... in lba_legacy_resources()
1249 * f4008000-f40083ff : tulip in lba_legacy_resources()
1250 * f4800000-f4ffffff : PCI01 LMMIO in lba_legacy_resources()
1251 * f6000000-f67fffff : PCI02 LMMIO in lba_legacy_resources()
1252 * f7000000-f77fffff : PCI03 LMMIO in lba_legacy_resources()
1253 * f9000000-f9ffffff : PCI02 ELMMIO in lba_legacy_resources()
1254 * fa000000-fbffffff : PCI03 ELMMIO in lba_legacy_resources()
1255 * fa100000-fa4fffff : stifb mmio in lba_legacy_resources()
1256 * fb000000-fb1fffff : stifb fb in lba_legacy_resources()
1258 * ie all Built-in core are under now correctly under PCI00. in lba_legacy_resources()
1260 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2 in lba_legacy_resources()
1264 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); in lba_legacy_resources()
1265 if (r->start & 1) { in lba_legacy_resources()
1268 r->flags = IORESOURCE_MEM; in lba_legacy_resources()
1270 r->start &= mmio_mask; in lba_legacy_resources()
1271 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); in lba_legacy_resources()
1272 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); in lba_legacy_resources()
1279 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start); in lba_legacy_resources()
1280 r->end = r->start + rsize; in lba_legacy_resources()
1282 r->end = r->start = 0; /* Not enabled. */ in lba_legacy_resources()
1301 r = &(lba_dev->hba.elmmio_space); in lba_legacy_resources()
1302 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO", in lba_legacy_resources()
1303 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1304 r->name = lba_dev->hba.elmmio_name; in lba_legacy_resources()
1310 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); in lba_legacy_resources()
1312 if (r->start & 1) { in lba_legacy_resources()
1314 r->flags = IORESOURCE_MEM; in lba_legacy_resources()
1316 r->start &= mmio_mask; in lba_legacy_resources()
1317 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); in lba_legacy_resources()
1318 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); in lba_legacy_resources()
1319 r->end = r->start + ~rsize; in lba_legacy_resources()
1323 r = &(lba_dev->hba.io_space); in lba_legacy_resources()
1324 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", in lba_legacy_resources()
1325 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1326 r->name = lba_dev->hba.io_name; in lba_legacy_resources()
1327 r->flags = IORESOURCE_IO; in lba_legacy_resources()
1328 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; in lba_legacy_resources()
1329 …r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - … in lba_legacy_resources()
1332 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); in lba_legacy_resources()
1333 r->start |= lba_num; in lba_legacy_resources()
1334 r->end |= lba_num; in lba_legacy_resources()
1358 d->hba.base_addr, in lba_hw_init()
1359 READ_REG64(d->hba.base_addr + LBA_STAT_CTL), in lba_hw_init()
1360 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), in lba_hw_init()
1361 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), in lba_hw_init()
1362 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); in lba_hw_init()
1364 READ_REG64(d->hba.base_addr + LBA_ARB_MASK), in lba_hw_init()
1365 READ_REG64(d->hba.base_addr + LBA_ARB_PRI), in lba_hw_init()
1366 READ_REG64(d->hba.base_addr + LBA_ARB_MODE), in lba_hw_init()
1367 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); in lba_hw_init()
1369 READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); in lba_hw_init()
1373 printk(" %Lx", READ_REG64(d->hba.base_addr + i)); in lba_hw_init()
1380 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support in lba_hw_init()
1381 * Only N-Class and up can really make use of Get slot status. in lba_hw_init()
1382 * maybe L-class too but I've never played with it there. in lba_hw_init()
1387 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; in lba_hw_init()
1392 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); in lba_hw_init()
1396 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); in lba_hw_init()
1403 * "Master Abort" means the MMIO transaction timed out - usually due to in lba_hw_init()
1412 * Soft Faul mode on PA-RISC now too. in lba_hw_init()
1414 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1416 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1418 WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1429 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { in lba_hw_init()
1440 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); in lba_hw_init()
1456 * number will be taken care of by the PCI-PCI bridge.
1478 addr = ioremap(dev->hpa.start, 4096); in lba_driver_probe()
1480 return -ENOMEM; in lba_driver_probe()
1498 version, func_class & 0xf, (long)dev->hpa.start); in lba_driver_probe()
1502 "TR2.1 - continuing under adversity.\n"); in lba_driver_probe()
1528 minor, func_class, (long)dev->hpa.start); in lba_driver_probe()
1533 (long)dev->hpa.start); in lba_driver_probe()
1534 return -ENODEV; in lba_driver_probe()
1538 tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE, in lba_driver_probe()
1547 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n"); in lba_driver_probe()
1552 /* ---------- First : initialize data we already have --------- */ in lba_driver_probe()
1554 lba_dev->hw_rev = func_class; in lba_driver_probe()
1555 lba_dev->hba.base_addr = addr; in lba_driver_probe()
1556 lba_dev->hba.dev = dev; in lba_driver_probe()
1557 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */ in lba_driver_probe()
1558 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ in lba_driver_probe()
1561 /* ------------ Second : initialize common stuff ---------- */ in lba_driver_probe()
1563 pcibios_register_hba(&lba_dev->hba); in lba_driver_probe()
1564 spin_lock_init(&lba_dev->lba_lock); in lba_driver_probe()
1569 /* ---------- Third : setup I/O Port and MMIO resources --------- */ in lba_driver_probe()
1587 if (lba_dev->hba.bus_num.start < lba_next_bus) in lba_driver_probe()
1588 lba_dev->hba.bus_num.start = lba_next_bus; in lba_driver_probe()
1600 &(lba_dev->hba.lmmio_space))) { in lba_driver_probe()
1602 (long)lba_dev->hba.lmmio_space.start, in lba_driver_probe()
1603 (long)lba_dev->hba.lmmio_space.end); in lba_driver_probe()
1604 lba_dev->hba.lmmio_space.flags = 0; in lba_driver_probe()
1607 pci_add_resource_offset(&resources, &lba_dev->hba.io_space, in lba_driver_probe()
1608 HBA_PORT_BASE(lba_dev->hba.hba_num)); in lba_driver_probe()
1609 if (lba_dev->hba.elmmio_space.flags) in lba_driver_probe()
1610 pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space, in lba_driver_probe()
1611 lba_dev->hba.lmmio_space_offset); in lba_driver_probe()
1612 if (lba_dev->hba.lmmio_space.flags) in lba_driver_probe()
1613 pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space, in lba_driver_probe()
1614 lba_dev->hba.lmmio_space_offset); in lba_driver_probe()
1615 if (lba_dev->hba.gmmio_space.flags) { in lba_driver_probe()
1616 /* Not registering GMMIO space - according to docs it's not in lba_driver_probe()
1617 * even used on HP-UX. */ in lba_driver_probe()
1618 /* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */ in lba_driver_probe()
1621 pci_add_resource(&resources, &lba_dev->hba.bus_num); in lba_driver_probe()
1623 dev->dev.platform_data = lba_dev; in lba_driver_probe()
1624 lba_bus = lba_dev->hba.hba_bus = in lba_driver_probe()
1625 pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start, in lba_driver_probe()
1636 /* assign resources to un-initialized devices */ in lba_driver_probe()
1646 lba_dump_res(&lba_dev->hba.io_space, 2); in lba_driver_probe()
1648 lba_dump_res(&lba_dev->hba.lmmio_space, 2); in lba_driver_probe()
1658 lba_dev->flags |= LBA_FLAG_SKIP_PROBE; in lba_driver_probe()
1698 void __iomem * base_addr = ioremap(lba->hpa.start, 4096); in lba_set_iregs()
1700 imask <<= 2; /* adjust for hints - 2 more bits */ in lba_set_iregs()
1715 * seems rushed, so that many built-in components simply don't work.
1716 * The following quirks disable the serial AUX port and the built-in ATI RV100
1724 if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || in quirk_diva_ati_card()
1725 dev->subsystem_device != 0x1292) in quirk_diva_ati_card()
1728 dev_info(&dev->dev, "Hiding Diva built-in ATI card"); in quirk_diva_ati_card()
1729 dev->device = 0; in quirk_diva_ati_card()
1736 if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || in quirk_diva_aux_disable()
1737 dev->subsystem_device != 0x1291) in quirk_diva_aux_disable()
1740 dev_info(&dev->dev, "Hiding Diva built-in AUX serial device"); in quirk_diva_aux_disable()
1741 dev->device = 0; in quirk_diva_aux_disable()
1748 if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || in quirk_tosca_aux_disable()
1749 dev->subsystem_device != 0x104a) in quirk_tosca_aux_disable()
1752 dev_info(&dev->dev, "Hiding Tosca secondary built-in AUX serial device"); in quirk_tosca_aux_disable()
1753 dev->device = 0; in quirk_tosca_aux_disable()