Lines Matching +full:msi +full:- +full:base +full:- +full:vec
9 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
19 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
66 #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
74 #define bar0_off(base, bar) ((base) + ((bar) << 2)) argument
75 #define bar2_off(base, bar) bar0_off(base, (bar) - 2) argument
88 static int b2b_mw_idx = -1;
105 "XEON B2B USD BAR 2 64-bit address");
110 "XEON B2B USD BAR 4 64-bit address");
115 "XEON B2B USD split-BAR 4 32-bit address");
120 "XEON B2B USD split-BAR 5 32-bit address");
125 "XEON B2B DSD BAR 2 64-bit address");
130 "XEON B2B DSD BAR 4 64-bit address");
135 "XEON B2B DSD split-BAR 4 32-bit address");
140 "XEON B2B DSD split-BAR 5 32-bit address");
147 ndev->unsafe_flags = 0; in ndev_reset_unsafe_flags()
148 ndev->unsafe_flags_ignore = 0; in ndev_reset_unsafe_flags()
151 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) in ndev_reset_unsafe_flags()
152 if (!ntb_topo_is_b2b(ndev->ntb.topo)) in ndev_reset_unsafe_flags()
153 ndev->unsafe_flags |= NTB_UNSAFE_DB; in ndev_reset_unsafe_flags()
156 if (ndev->hwerr_flags & NTB_HWERR_SB01BASE_LOCKUP) { in ndev_reset_unsafe_flags()
157 ndev->unsafe_flags |= NTB_UNSAFE_DB; in ndev_reset_unsafe_flags()
158 ndev->unsafe_flags |= NTB_UNSAFE_SPAD; in ndev_reset_unsafe_flags()
165 return !!(flag & ndev->unsafe_flags & ~ndev->unsafe_flags_ignore); in ndev_is_unsafe()
171 flag &= ndev->unsafe_flags; in ndev_ignore_unsafe()
172 ndev->unsafe_flags_ignore |= flag; in ndev_ignore_unsafe()
179 if (idx < 0 || idx >= ndev->mw_count) in ndev_mw_to_bar()
180 return -EINVAL; in ndev_mw_to_bar()
181 return ndev->reg->mw_bar[idx]; in ndev_mw_to_bar()
193 dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx\n", *db_addr); in ndev_db_addr()
197 *db_size = ndev->reg->db_size; in ndev_db_addr()
198 dev_dbg(&ndev->ntb.pdev->dev, "Peer db size %llx\n", *db_size); in ndev_db_addr()
208 return ndev->reg->db_ioread(mmio); in ndev_db_read()
217 if (db_bits & ~ndev->db_valid_mask) in ndev_db_write()
218 return -EINVAL; in ndev_db_write()
220 ndev->reg->db_iowrite(db_bits, mmio); in ndev_db_write()
233 if (db_bits & ~ndev->db_valid_mask) in ndev_db_set_mask()
234 return -EINVAL; in ndev_db_set_mask()
236 spin_lock_irqsave(&ndev->db_mask_lock, irqflags); in ndev_db_set_mask()
238 ndev->db_mask |= db_bits; in ndev_db_set_mask()
239 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_set_mask()
241 spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags); in ndev_db_set_mask()
254 if (db_bits & ~ndev->db_valid_mask) in ndev_db_clear_mask()
255 return -EINVAL; in ndev_db_clear_mask()
257 spin_lock_irqsave(&ndev->db_mask_lock, irqflags); in ndev_db_clear_mask()
259 ndev->db_mask &= ~db_bits; in ndev_db_clear_mask()
260 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_clear_mask()
262 spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags); in ndev_db_clear_mask()
271 shift = ndev->db_vec_shift; in ndev_vec_mask()
272 mask = BIT_ULL(shift) - 1; in ndev_vec_mask()
284 if (idx < 0 || idx >= ndev->spad_count) in ndev_spad_addr()
285 return -EINVAL; in ndev_spad_addr()
289 dev_dbg(&ndev->ntb.pdev->dev, "Peer spad addr %llx\n", in ndev_spad_addr()
302 if (idx < 0 || idx >= ndev->spad_count) in ndev_spad_read()
314 if (idx < 0 || idx >= ndev->spad_count) in ndev_spad_write()
315 return -EINVAL; in ndev_spad_write()
322 static irqreturn_t ndev_interrupt(struct intel_ntb_dev *ndev, int vec) in ndev_interrupt() argument
326 vec_mask = ndev_vec_mask(ndev, vec); in ndev_interrupt()
328 if ((ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) && (vec == 31)) in ndev_interrupt()
329 vec_mask |= ndev->db_link_mask; in ndev_interrupt()
331 dev_dbg(&ndev->ntb.pdev->dev, "vec %d vec_mask %llx\n", vec, vec_mask); in ndev_interrupt()
333 ndev->last_ts = jiffies; in ndev_interrupt()
335 if (vec_mask & ndev->db_link_mask) { in ndev_interrupt()
336 if (ndev->reg->poll_link(ndev)) in ndev_interrupt()
337 ntb_link_event(&ndev->ntb); in ndev_interrupt()
340 if (vec_mask & ndev->db_valid_mask) in ndev_interrupt()
341 ntb_db_event(&ndev->ntb, vec); in ndev_interrupt()
350 dev_dbg(&nvec->ndev->ntb.pdev->dev, "irq: %d nvec->num: %d\n", in ndev_vec_isr()
351 irq, nvec->num); in ndev_vec_isr()
353 return ndev_interrupt(nvec->ndev, nvec->num); in ndev_vec_isr()
360 return ndev_interrupt(ndev, irq - ndev->ntb.pdev->irq); in ndev_irq_isr()
370 pdev = ndev->ntb.pdev; in ndev_init_isr()
372 node = dev_to_node(&pdev->dev); in ndev_init_isr()
375 ndev->db_mask = ndev->db_valid_mask; in ndev_init_isr()
376 ndev->reg->db_iowrite(ndev->db_mask, in ndev_init_isr()
377 ndev->self_mmio + in ndev_init_isr()
378 ndev->self_reg->db_mask); in ndev_init_isr()
382 ndev->vec = kcalloc_node(msix_max, sizeof(*ndev->vec), in ndev_init_isr()
384 if (!ndev->vec) in ndev_init_isr()
387 ndev->msix = kcalloc_node(msix_max, sizeof(*ndev->msix), in ndev_init_isr()
389 if (!ndev->msix) in ndev_init_isr()
393 ndev->msix[i].entry = i; in ndev_init_isr()
395 msix_count = pci_enable_msix_range(pdev, ndev->msix, in ndev_init_isr()
401 ndev->vec[i].ndev = ndev; in ndev_init_isr()
402 ndev->vec[i].num = i; in ndev_init_isr()
403 rc = request_irq(ndev->msix[i].vector, ndev_vec_isr, 0, in ndev_init_isr()
404 "ndev_vec_isr", &ndev->vec[i]); in ndev_init_isr()
409 dev_dbg(&pdev->dev, "Using %d msix interrupts\n", msix_count); in ndev_init_isr()
410 ndev->db_vec_count = msix_count; in ndev_init_isr()
411 ndev->db_vec_shift = msix_shift; in ndev_init_isr()
415 while (i-- > 0) in ndev_init_isr()
416 free_irq(ndev->msix[i].vector, &ndev->vec[i]); in ndev_init_isr()
419 kfree(ndev->msix); in ndev_init_isr()
421 kfree(ndev->vec); in ndev_init_isr()
423 ndev->msix = NULL; in ndev_init_isr()
424 ndev->vec = NULL; in ndev_init_isr()
426 /* Try to set up msi irq */ in ndev_init_isr()
432 rc = request_irq(pdev->irq, ndev_irq_isr, 0, in ndev_init_isr()
437 dev_dbg(&pdev->dev, "Using msi interrupts\n"); in ndev_init_isr()
438 ndev->db_vec_count = 1; in ndev_init_isr()
439 ndev->db_vec_shift = total_shift; in ndev_init_isr()
450 rc = request_irq(pdev->irq, ndev_irq_isr, IRQF_SHARED, in ndev_init_isr()
455 dev_dbg(&pdev->dev, "Using intx interrupts\n"); in ndev_init_isr()
456 ndev->db_vec_count = 1; in ndev_init_isr()
457 ndev->db_vec_shift = total_shift; in ndev_init_isr()
469 pdev = ndev->ntb.pdev; in ndev_deinit_isr()
472 ndev->db_mask = ndev->db_valid_mask; in ndev_deinit_isr()
473 ndev->reg->db_iowrite(ndev->db_mask, in ndev_deinit_isr()
474 ndev->self_mmio + in ndev_deinit_isr()
475 ndev->self_reg->db_mask); in ndev_deinit_isr()
477 if (ndev->msix) { in ndev_deinit_isr()
478 i = ndev->db_vec_count; in ndev_deinit_isr()
479 while (i--) in ndev_deinit_isr()
480 free_irq(ndev->msix[i].vector, &ndev->vec[i]); in ndev_deinit_isr()
482 kfree(ndev->msix); in ndev_deinit_isr()
483 kfree(ndev->vec); in ndev_deinit_isr()
485 free_irq(pdev->irq, ndev); in ndev_deinit_isr()
502 ndev = filp->private_data; in ndev_ntb_debugfs_read()
503 pdev = ndev->ntb.pdev; in ndev_ntb_debugfs_read()
504 mmio = ndev->self_mmio; in ndev_ntb_debugfs_read()
510 return -ENOMEM; in ndev_ntb_debugfs_read()
514 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
517 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
518 "Connection Topology -\t%s\n", in ndev_ntb_debugfs_read()
519 ntb_topo_string(ndev->ntb.topo)); in ndev_ntb_debugfs_read()
521 if (ndev->b2b_idx != UINT_MAX) { in ndev_ntb_debugfs_read()
522 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
523 "B2B MW Idx -\t\t%u\n", ndev->b2b_idx); in ndev_ntb_debugfs_read()
524 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
525 "B2B Offset -\t\t%#lx\n", ndev->b2b_off); in ndev_ntb_debugfs_read()
528 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
529 "BAR4 Split -\t\t%s\n", in ndev_ntb_debugfs_read()
530 ndev->bar4_split ? "yes" : "no"); in ndev_ntb_debugfs_read()
532 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
533 "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl); in ndev_ntb_debugfs_read()
534 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
535 "LNK STA -\t\t%#06x\n", ndev->lnk_sta); in ndev_ntb_debugfs_read()
537 if (!ndev->reg->link_is_up(ndev)) { in ndev_ntb_debugfs_read()
538 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
539 "Link Status -\t\tDown\n"); in ndev_ntb_debugfs_read()
541 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
542 "Link Status -\t\tUp\n"); in ndev_ntb_debugfs_read()
543 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
544 "Link Speed -\t\tPCI-E Gen %u\n", in ndev_ntb_debugfs_read()
545 NTB_LNK_STA_SPEED(ndev->lnk_sta)); in ndev_ntb_debugfs_read()
546 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
547 "Link Width -\t\tx%u\n", in ndev_ntb_debugfs_read()
548 NTB_LNK_STA_WIDTH(ndev->lnk_sta)); in ndev_ntb_debugfs_read()
551 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
552 "Memory Window Count -\t%u\n", ndev->mw_count); in ndev_ntb_debugfs_read()
553 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
554 "Scratchpad Count -\t%u\n", ndev->spad_count); in ndev_ntb_debugfs_read()
555 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
556 "Doorbell Count -\t%u\n", ndev->db_count); in ndev_ntb_debugfs_read()
557 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
558 "Doorbell Vector Count -\t%u\n", ndev->db_vec_count); in ndev_ntb_debugfs_read()
559 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
560 "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift); in ndev_ntb_debugfs_read()
562 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
563 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask); in ndev_ntb_debugfs_read()
564 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
565 "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask); in ndev_ntb_debugfs_read()
566 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
567 "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask); in ndev_ntb_debugfs_read()
569 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); in ndev_ntb_debugfs_read()
570 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
571 "Doorbell Mask -\t\t%#llx\n", u.v64); in ndev_ntb_debugfs_read()
573 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell); in ndev_ntb_debugfs_read()
574 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
575 "Doorbell Bell -\t\t%#llx\n", u.v64); in ndev_ntb_debugfs_read()
577 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
581 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
583 if (!ndev->bar4_split) { in ndev_ntb_debugfs_read()
585 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
589 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
592 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
597 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
599 if (!ndev->bar4_split) { in ndev_ntb_debugfs_read()
601 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
605 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
608 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
612 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
615 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2)); in ndev_ntb_debugfs_read()
616 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
617 "XLAT23 -\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
619 if (ndev->bar4_split) { in ndev_ntb_debugfs_read()
620 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4)); in ndev_ntb_debugfs_read()
621 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
622 "XLAT4 -\t\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
624 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 5)); in ndev_ntb_debugfs_read()
625 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
626 "XLAT5 -\t\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
628 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4)); in ndev_ntb_debugfs_read()
629 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
630 "XLAT45 -\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
633 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2)); in ndev_ntb_debugfs_read()
634 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
635 "LMT23 -\t\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
637 if (ndev->bar4_split) { in ndev_ntb_debugfs_read()
638 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4)); in ndev_ntb_debugfs_read()
639 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
640 "LMT4 -\t\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
641 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 5)); in ndev_ntb_debugfs_read()
642 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
643 "LMT5 -\t\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
645 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4)); in ndev_ntb_debugfs_read()
646 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
647 "LMT45 -\t\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
651 if (ntb_topo_is_b2b(ndev->ntb.topo)) { in ndev_ntb_debugfs_read()
652 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
656 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
657 "B2B XLAT23 -\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
659 if (ndev->bar4_split) { in ndev_ntb_debugfs_read()
661 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
662 "B2B XLAT4 -\t\t%#06x\n", in ndev_ntb_debugfs_read()
665 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
666 "B2B XLAT5 -\t\t%#06x\n", in ndev_ntb_debugfs_read()
670 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
671 "B2B XLAT45 -\t\t%#018llx\n", in ndev_ntb_debugfs_read()
676 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
677 "B2B LMT23 -\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
679 if (ndev->bar4_split) { in ndev_ntb_debugfs_read()
681 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
682 "B2B LMT4 -\t\t%#06x\n", in ndev_ntb_debugfs_read()
685 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
686 "B2B LMT5 -\t\t%#06x\n", in ndev_ntb_debugfs_read()
690 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
691 "B2B LMT45 -\t\t%#018llx\n", in ndev_ntb_debugfs_read()
695 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
699 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
700 "SBAR01 -\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
703 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
704 "SBAR23 -\t\t%#018llx\n", u.v64); in ndev_ntb_debugfs_read()
706 if (ndev->bar4_split) { in ndev_ntb_debugfs_read()
708 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
709 "SBAR4 -\t\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
711 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
712 "SBAR5 -\t\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
715 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
716 "SBAR45 -\t\t%#018llx\n", in ndev_ntb_debugfs_read()
721 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
725 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
726 "Upstream Memory Miss -\t%u\n", u.v16); in ndev_ntb_debugfs_read()
728 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
733 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
734 "DEVSTS -\t\t%#06x\n", u.v16); in ndev_ntb_debugfs_read()
738 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
739 "LNKSTS -\t\t%#06x\n", u.v16); in ndev_ntb_debugfs_read()
743 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
744 "UNCERRSTS -\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
748 off += scnprintf(buf + off, buf_size - off, in ndev_ntb_debugfs_read()
749 "CORERRSTS -\t\t%#06x\n", u.v32); in ndev_ntb_debugfs_read()
760 struct intel_ntb_dev *ndev = filp->private_data; in ndev_debugfs_read()
762 if (pdev_is_gen1(ndev->ntb.pdev)) in ndev_debugfs_read()
764 else if (pdev_is_gen3(ndev->ntb.pdev)) in ndev_debugfs_read()
766 else if (pdev_is_gen4(ndev->ntb.pdev) || pdev_is_gen5(ndev->ntb.pdev)) in ndev_debugfs_read()
769 return -ENXIO; in ndev_debugfs_read()
775 ndev->debugfs_dir = NULL; in ndev_init_debugfs()
776 ndev->debugfs_info = NULL; in ndev_init_debugfs()
778 ndev->debugfs_dir = in ndev_init_debugfs()
779 debugfs_create_dir(pci_name(ndev->ntb.pdev), in ndev_init_debugfs()
781 if (IS_ERR(ndev->debugfs_dir)) in ndev_init_debugfs()
782 ndev->debugfs_info = NULL; in ndev_init_debugfs()
784 ndev->debugfs_info = in ndev_init_debugfs()
786 ndev->debugfs_dir, ndev, in ndev_init_debugfs()
793 debugfs_remove_recursive(ndev->debugfs_dir); in ndev_deinit_debugfs()
799 return -EINVAL; in intel_ntb_mw_count()
801 return ntb_ndev(ntb)->mw_count; in intel_ntb_mw_count()
814 return -EINVAL; in intel_ntb_mw_get_align()
816 if (idx >= ndev->b2b_idx && !ndev->b2b_off) in intel_ntb_mw_get_align()
823 bar_size = pci_resource_len(ndev->ntb.pdev, bar); in intel_ntb_mw_get_align()
825 if (idx == ndev->b2b_idx) in intel_ntb_mw_get_align()
826 mw_size = bar_size - ndev->b2b_off; in intel_ntb_mw_get_align()
831 *addr_align = pci_resource_len(ndev->ntb.pdev, bar); in intel_ntb_mw_get_align()
849 u64 base, limit, reg_val; in intel_ntb_mw_set_trans() local
853 return -EINVAL; in intel_ntb_mw_set_trans()
855 if (idx >= ndev->b2b_idx && !ndev->b2b_off) in intel_ntb_mw_set_trans()
862 bar_size = pci_resource_len(ndev->ntb.pdev, bar); in intel_ntb_mw_set_trans()
864 if (idx == ndev->b2b_idx) in intel_ntb_mw_set_trans()
865 mw_size = bar_size - ndev->b2b_off; in intel_ntb_mw_set_trans()
870 if (addr & (bar_size - 1)) in intel_ntb_mw_set_trans()
871 return -EINVAL; in intel_ntb_mw_set_trans()
875 return -EINVAL; in intel_ntb_mw_set_trans()
877 mmio = ndev->self_mmio; in intel_ntb_mw_set_trans()
878 base_reg = bar0_off(ndev->xlat_reg->bar0_base, bar); in intel_ntb_mw_set_trans()
879 xlat_reg = bar2_off(ndev->xlat_reg->bar2_xlat, bar); in intel_ntb_mw_set_trans()
880 limit_reg = bar2_off(ndev->xlat_reg->bar2_limit, bar); in intel_ntb_mw_set_trans()
882 if (bar < 4 || !ndev->bar4_split) { in intel_ntb_mw_set_trans()
883 base = ioread64(mmio + base_reg) & NTB_BAR_MASK_64; in intel_ntb_mw_set_trans()
887 limit = base + size; in intel_ntb_mw_set_trans()
896 return -EIO; in intel_ntb_mw_set_trans()
903 iowrite64(base, mmio + limit_reg); in intel_ntb_mw_set_trans()
905 return -EIO; in intel_ntb_mw_set_trans()
910 return -EINVAL; in intel_ntb_mw_set_trans()
912 return -EINVAL; in intel_ntb_mw_set_trans()
914 base = ioread32(mmio + base_reg) & NTB_BAR_MASK_32; in intel_ntb_mw_set_trans()
918 limit = base + size; in intel_ntb_mw_set_trans()
927 return -EIO; in intel_ntb_mw_set_trans()
934 iowrite32(base, mmio + limit_reg); in intel_ntb_mw_set_trans()
936 return -EIO; in intel_ntb_mw_set_trans()
948 if (ndev->reg->link_is_up(ndev)) { in intel_ntb_link_is_up()
950 *speed = NTB_LNK_STA_SPEED(ndev->lnk_sta); in intel_ntb_link_is_up()
952 *width = NTB_LNK_STA_WIDTH(ndev->lnk_sta); in intel_ntb_link_is_up()
974 if (ndev->ntb.topo == NTB_TOPO_SEC) in intel_ntb_link_enable()
975 return -EINVAL; in intel_ntb_link_enable()
977 dev_dbg(&ntb->pdev->dev, in intel_ntb_link_enable()
981 dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed); in intel_ntb_link_enable()
983 dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width); in intel_ntb_link_enable()
985 ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); in intel_ntb_link_enable()
989 if (ndev->bar4_split) in intel_ntb_link_enable()
991 iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); in intel_ntb_link_enable()
1003 if (ndev->ntb.topo == NTB_TOPO_SEC) in intel_ntb_link_disable()
1004 return -EINVAL; in intel_ntb_link_disable()
1006 dev_dbg(&ntb->pdev->dev, "Disabling link\n"); in intel_ntb_link_disable()
1009 ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); in intel_ntb_link_disable()
1012 if (ndev->bar4_split) in intel_ntb_link_disable()
1015 iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl); in intel_ntb_link_disable()
1023 return ntb_ndev(ntb)->mw_count; in intel_ntb_peer_mw_count()
1027 phys_addr_t *base, resource_size_t *size) in intel_ntb_peer_mw_get_addr() argument
1032 if (idx >= ndev->b2b_idx && !ndev->b2b_off) in intel_ntb_peer_mw_get_addr()
1039 if (base) in intel_ntb_peer_mw_get_addr()
1040 *base = pci_resource_start(ndev->ntb.pdev, bar) + in intel_ntb_peer_mw_get_addr()
1041 (idx == ndev->b2b_idx ? ndev->b2b_off : 0); in intel_ntb_peer_mw_get_addr()
1044 *size = pci_resource_len(ndev->ntb.pdev, bar) - in intel_ntb_peer_mw_get_addr()
1045 (idx == ndev->b2b_idx ? ndev->b2b_off : 0); in intel_ntb_peer_mw_get_addr()
1057 return ntb_ndev(ntb)->db_valid_mask; in intel_ntb_db_valid_mask()
1066 return ndev->db_vec_count; in intel_ntb_db_vector_count()
1073 if (db_vector < 0 || db_vector > ndev->db_vec_count) in intel_ntb_db_vector_mask()
1076 return ndev->db_valid_mask & ndev_vec_mask(ndev, db_vector); in intel_ntb_db_vector_mask()
1084 ndev->self_mmio + in intel_ntb_db_read()
1085 ndev->self_reg->db_bell); in intel_ntb_db_read()
1093 ndev->self_mmio + in intel_ntb_db_clear()
1094 ndev->self_reg->db_bell); in intel_ntb_db_clear()
1102 ndev->self_mmio + in intel_ntb_db_set_mask()
1103 ndev->self_reg->db_mask); in intel_ntb_db_set_mask()
1111 ndev->self_mmio + in intel_ntb_db_clear_mask()
1112 ndev->self_reg->db_mask); in intel_ntb_db_clear_mask()
1122 return -EINVAL; in intel_ntb_peer_db_addr()
1126 if (unlikely(db_bits & ~ntb_ndev(ntb)->db_valid_mask)) in intel_ntb_peer_db_addr()
1127 return -EINVAL; in intel_ntb_peer_db_addr()
1129 ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr, in intel_ntb_peer_db_addr()
1130 ndev->peer_reg->db_bell); in intel_ntb_peer_db_addr()
1144 ndev->peer_mmio + in intel_ntb_peer_db_set()
1145 ndev->peer_reg->db_bell); in intel_ntb_peer_db_set()
1159 return ndev->spad_count; in intel_ntb_spad_count()
1167 ndev->self_mmio + in intel_ntb_spad_read()
1168 ndev->self_reg->spad); in intel_ntb_spad_read()
1176 ndev->self_mmio + in intel_ntb_spad_write()
1177 ndev->self_reg->spad); in intel_ntb_spad_write()
1185 return ndev_spad_addr(ndev, sidx, spad_addr, ndev->peer_addr, in intel_ntb_peer_spad_addr()
1186 ndev->peer_reg->spad); in intel_ntb_peer_spad_addr()
1194 ndev->peer_mmio + in intel_ntb_peer_spad_read()
1195 ndev->peer_reg->spad); in intel_ntb_peer_spad_read()
1204 ndev->peer_mmio + in intel_ntb_peer_spad_write()
1205 ndev->peer_reg->spad); in intel_ntb_peer_spad_write()
1223 ndev->reg->db_iowrite(ndev->db_link_mask, in xeon_poll_link()
1224 ndev->self_mmio + in xeon_poll_link()
1225 ndev->self_reg->db_bell); in xeon_poll_link()
1227 rc = pci_read_config_word(ndev->ntb.pdev, in xeon_poll_link()
1232 if (reg_val == ndev->lnk_sta) in xeon_poll_link()
1235 ndev->lnk_sta = reg_val; in xeon_poll_link()
1242 if (ndev->ntb.topo == NTB_TOPO_SEC) in xeon_link_is_up()
1245 return NTB_LNK_STA_ACTIVE(ndev->lnk_sta); in xeon_link_is_up()
1272 dev_dbg(&ndev->ntb.pdev->dev, "PPD %d split bar\n", ppd); in xeon_ppd_bar4_split()
1302 pdev = ndev->ntb.pdev; in xeon_setup_b2b_mw()
1303 mmio = ndev->self_mmio; in xeon_setup_b2b_mw()
1305 if (ndev->b2b_idx == UINT_MAX) { in xeon_setup_b2b_mw()
1306 dev_dbg(&pdev->dev, "not using b2b mw\n"); in xeon_setup_b2b_mw()
1308 ndev->b2b_off = 0; in xeon_setup_b2b_mw()
1310 b2b_bar = ndev_mw_to_bar(ndev, ndev->b2b_idx); in xeon_setup_b2b_mw()
1312 return -EIO; in xeon_setup_b2b_mw()
1314 dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar); in xeon_setup_b2b_mw()
1316 bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar); in xeon_setup_b2b_mw()
1318 dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size); in xeon_setup_b2b_mw()
1321 dev_dbg(&pdev->dev, "b2b using first half of bar\n"); in xeon_setup_b2b_mw()
1322 ndev->b2b_off = bar_size >> 1; in xeon_setup_b2b_mw()
1324 dev_dbg(&pdev->dev, "b2b using whole bar\n"); in xeon_setup_b2b_mw()
1325 ndev->b2b_off = 0; in xeon_setup_b2b_mw()
1326 --ndev->mw_count; in xeon_setup_b2b_mw()
1328 dev_dbg(&pdev->dev, "b2b bar size is too small\n"); in xeon_setup_b2b_mw()
1329 return -EIO; in xeon_setup_b2b_mw()
1340 dev_dbg(&pdev->dev, "PBAR23SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1342 if (ndev->b2b_off) in xeon_setup_b2b_mw()
1343 bar_sz -= 1; in xeon_setup_b2b_mw()
1349 dev_dbg(&pdev->dev, "SBAR23SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1351 if (!ndev->bar4_split) { in xeon_setup_b2b_mw()
1353 dev_dbg(&pdev->dev, "PBAR45SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1355 if (ndev->b2b_off) in xeon_setup_b2b_mw()
1356 bar_sz -= 1; in xeon_setup_b2b_mw()
1362 dev_dbg(&pdev->dev, "SBAR45SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1365 dev_dbg(&pdev->dev, "PBAR4SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1367 if (ndev->b2b_off) in xeon_setup_b2b_mw()
1368 bar_sz -= 1; in xeon_setup_b2b_mw()
1374 dev_dbg(&pdev->dev, "SBAR4SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1377 dev_dbg(&pdev->dev, "PBAR5SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1379 if (ndev->b2b_off) in xeon_setup_b2b_mw()
1380 bar_sz -= 1; in xeon_setup_b2b_mw()
1386 dev_dbg(&pdev->dev, "SBAR5SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1391 bar_addr = addr->bar0_addr; in xeon_setup_b2b_mw()
1393 bar_addr = addr->bar2_addr64; in xeon_setup_b2b_mw()
1394 else if (b2b_bar == 4 && !ndev->bar4_split) in xeon_setup_b2b_mw()
1395 bar_addr = addr->bar4_addr64; in xeon_setup_b2b_mw()
1397 bar_addr = addr->bar4_addr32; in xeon_setup_b2b_mw()
1399 bar_addr = addr->bar5_addr32; in xeon_setup_b2b_mw()
1401 return -EIO; in xeon_setup_b2b_mw()
1403 dev_dbg(&pdev->dev, "SBAR01 %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1407 * The b2b bar is either disabled above, or configured half-size, and in xeon_setup_b2b_mw()
1411 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1414 dev_dbg(&pdev->dev, "SBAR23 %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1416 if (!ndev->bar4_split) { in xeon_setup_b2b_mw()
1417 bar_addr = addr->bar4_addr64 + in xeon_setup_b2b_mw()
1418 (b2b_bar == 4 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1421 dev_dbg(&pdev->dev, "SBAR45 %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1423 bar_addr = addr->bar4_addr32 + in xeon_setup_b2b_mw()
1424 (b2b_bar == 4 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1427 dev_dbg(&pdev->dev, "SBAR4 %#010llx\n", bar_addr); in xeon_setup_b2b_mw()
1429 bar_addr = addr->bar5_addr32 + in xeon_setup_b2b_mw()
1430 (b2b_bar == 5 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1433 dev_dbg(&pdev->dev, "SBAR5 %#010llx\n", bar_addr); in xeon_setup_b2b_mw()
1436 /* setup incoming bar limits == base addrs (zero length windows) */ in xeon_setup_b2b_mw()
1438 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1441 dev_dbg(&pdev->dev, "SBAR23LMT %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1443 if (!ndev->bar4_split) { in xeon_setup_b2b_mw()
1444 bar_addr = addr->bar4_addr64 + in xeon_setup_b2b_mw()
1445 (b2b_bar == 4 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1448 dev_dbg(&pdev->dev, "SBAR45LMT %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1450 bar_addr = addr->bar4_addr32 + in xeon_setup_b2b_mw()
1451 (b2b_bar == 4 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1454 dev_dbg(&pdev->dev, "SBAR4LMT %#010llx\n", bar_addr); in xeon_setup_b2b_mw()
1456 bar_addr = addr->bar5_addr32 + in xeon_setup_b2b_mw()
1457 (b2b_bar == 5 ? ndev->b2b_off : 0); in xeon_setup_b2b_mw()
1460 dev_dbg(&pdev->dev, "SBAR5LMT %#05llx\n", bar_addr); in xeon_setup_b2b_mw()
1466 if (!ndev->bar4_split) { in xeon_setup_b2b_mw()
1475 if (!ndev->bar4_split) { in xeon_setup_b2b_mw()
1483 bar_addr = peer_addr->bar2_addr64; in xeon_setup_b2b_mw()
1486 dev_dbg(&pdev->dev, "PBAR23XLAT %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1488 if (!ndev->bar4_split) { in xeon_setup_b2b_mw()
1489 bar_addr = peer_addr->bar4_addr64; in xeon_setup_b2b_mw()
1492 dev_dbg(&pdev->dev, "PBAR45XLAT %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1494 bar_addr = peer_addr->bar4_addr32; in xeon_setup_b2b_mw()
1497 dev_dbg(&pdev->dev, "PBAR4XLAT %#010llx\n", bar_addr); in xeon_setup_b2b_mw()
1499 bar_addr = peer_addr->bar5_addr32; in xeon_setup_b2b_mw()
1502 dev_dbg(&pdev->dev, "PBAR5XLAT %#010llx\n", bar_addr); in xeon_setup_b2b_mw()
1507 bar_addr = peer_addr->bar0_addr; in xeon_setup_b2b_mw()
1509 bar_addr = peer_addr->bar2_addr64; in xeon_setup_b2b_mw()
1510 else if (b2b_bar == 4 && !ndev->bar4_split) in xeon_setup_b2b_mw()
1511 bar_addr = peer_addr->bar4_addr64; in xeon_setup_b2b_mw()
1513 bar_addr = peer_addr->bar4_addr32; in xeon_setup_b2b_mw()
1515 bar_addr = peer_addr->bar5_addr32; in xeon_setup_b2b_mw()
1517 return -EIO; in xeon_setup_b2b_mw()
1520 dev_dbg(&pdev->dev, "B2BXLAT %#018llx\n", bar_addr); in xeon_setup_b2b_mw()
1526 ndev->peer_mmio = pci_iomap(pdev, b2b_bar, in xeon_setup_b2b_mw()
1528 if (!ndev->peer_mmio) in xeon_setup_b2b_mw()
1529 return -EIO; in xeon_setup_b2b_mw()
1531 ndev->peer_addr = pci_resource_start(pdev, b2b_bar); in xeon_setup_b2b_mw()
1539 struct device *dev = &ndev->ntb.pdev->dev; in xeon_init_ntb()
1543 if (ndev->bar4_split) in xeon_init_ntb()
1544 ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT; in xeon_init_ntb()
1546 ndev->mw_count = XEON_MW_COUNT; in xeon_init_ntb()
1548 ndev->spad_count = XEON_SPAD_COUNT; in xeon_init_ntb()
1549 ndev->db_count = XEON_DB_COUNT; in xeon_init_ntb()
1550 ndev->db_link_mask = XEON_DB_LINK_BIT; in xeon_init_ntb()
1552 switch (ndev->ntb.topo) { in xeon_init_ntb()
1554 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { in xeon_init_ntb()
1556 return -EINVAL; in xeon_init_ntb()
1560 ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); in xeon_init_ntb()
1562 iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); in xeon_init_ntb()
1565 ndev->spad_count >>= 1; in xeon_init_ntb()
1566 ndev->self_reg = &xeon_pri_reg; in xeon_init_ntb()
1567 ndev->peer_reg = &xeon_sec_reg; in xeon_init_ntb()
1568 ndev->xlat_reg = &xeon_sec_xlat; in xeon_init_ntb()
1572 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { in xeon_init_ntb()
1574 return -EINVAL; in xeon_init_ntb()
1577 ndev->spad_count >>= 1; in xeon_init_ntb()
1578 ndev->self_reg = &xeon_sec_reg; in xeon_init_ntb()
1579 ndev->peer_reg = &xeon_pri_reg; in xeon_init_ntb()
1580 ndev->xlat_reg = &xeon_pri_xlat; in xeon_init_ntb()
1585 ndev->self_reg = &xeon_pri_reg; in xeon_init_ntb()
1586 ndev->peer_reg = &xeon_b2b_reg; in xeon_init_ntb()
1587 ndev->xlat_reg = &xeon_sec_xlat; in xeon_init_ntb()
1589 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { in xeon_init_ntb()
1590 ndev->peer_reg = &xeon_pri_reg; in xeon_init_ntb()
1593 ndev->b2b_idx = b2b_mw_idx + ndev->mw_count; in xeon_init_ntb()
1595 ndev->b2b_idx = b2b_mw_idx; in xeon_init_ntb()
1597 if (ndev->b2b_idx >= ndev->mw_count) { in xeon_init_ntb()
1600 b2b_mw_idx, ndev->mw_count); in xeon_init_ntb()
1601 return -EINVAL; in xeon_init_ntb()
1605 b2b_mw_idx, ndev->b2b_idx); in xeon_init_ntb()
1607 } else if (ndev->hwerr_flags & NTB_HWERR_B2BDOORBELL_BIT14) { in xeon_init_ntb()
1609 ndev->db_count -= 1; in xeon_init_ntb()
1612 if (ndev->ntb.topo == NTB_TOPO_B2B_USD) { in xeon_init_ntb()
1626 ndev->self_mmio + XEON_SPCICMD_OFFSET); in xeon_init_ntb()
1631 return -EINVAL; in xeon_init_ntb()
1634 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; in xeon_init_ntb()
1636 ndev->reg->db_iowrite(ndev->db_valid_mask, in xeon_init_ntb()
1637 ndev->self_mmio + in xeon_init_ntb()
1638 ndev->self_reg->db_mask); in xeon_init_ntb()
1649 pdev = ndev->ntb.pdev; in xeon_init_dev()
1651 switch (pdev->device) { in xeon_init_dev()
1673 ndev->hwerr_flags |= NTB_HWERR_SDOORBELL_LOCKUP; in xeon_init_dev()
1677 switch (pdev->device) { in xeon_init_dev()
1690 ndev->hwerr_flags |= NTB_HWERR_SB01BASE_LOCKUP; in xeon_init_dev()
1694 switch (pdev->device) { in xeon_init_dev()
1714 ndev->hwerr_flags |= NTB_HWERR_B2BDOORBELL_BIT14; in xeon_init_dev()
1718 ndev->reg = &xeon_reg; in xeon_init_dev()
1722 return -EIO; in xeon_init_dev()
1724 ndev->ntb.topo = xeon_ppd_topo(ndev, ppd); in xeon_init_dev()
1725 dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd, in xeon_init_dev()
1726 ntb_topo_string(ndev->ntb.topo)); in xeon_init_dev()
1727 if (ndev->ntb.topo == NTB_TOPO_NONE) in xeon_init_dev()
1728 return -EINVAL; in xeon_init_dev()
1730 if (ndev->ntb.topo != NTB_TOPO_SEC) { in xeon_init_dev()
1731 ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd); in xeon_init_dev()
1732 dev_dbg(&pdev->dev, "ppd %#x bar4_split %d\n", in xeon_init_dev()
1733 ppd, ndev->bar4_split); in xeon_init_dev()
1740 ndev->bar4_split = hweight32(mem) == in xeon_init_dev()
1742 dev_dbg(&pdev->dev, "mem %#x bar4_split %d\n", in xeon_init_dev()
1743 mem, ndev->bar4_split); in xeon_init_dev()
1774 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in intel_ntb_init_pci()
1776 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in intel_ntb_init_pci()
1779 dev_warn(&pdev->dev, "Cannot DMA highmem\n"); in intel_ntb_init_pci()
1782 ndev->self_mmio = pci_iomap(pdev, 0, 0); in intel_ntb_init_pci()
1783 if (!ndev->self_mmio) { in intel_ntb_init_pci()
1784 rc = -EIO; in intel_ntb_init_pci()
1787 ndev->peer_mmio = ndev->self_mmio; in intel_ntb_init_pci()
1788 ndev->peer_addr = pci_resource_start(pdev, 0); in intel_ntb_init_pci()
1804 struct pci_dev *pdev = ndev->ntb.pdev; in intel_ntb_deinit_pci()
1806 if (ndev->peer_mmio && ndev->peer_mmio != ndev->self_mmio) in intel_ntb_deinit_pci()
1807 pci_iounmap(pdev, ndev->peer_mmio); in intel_ntb_deinit_pci()
1808 pci_iounmap(pdev, ndev->self_mmio); in intel_ntb_deinit_pci()
1818 ndev->ntb.pdev = pdev; in ndev_init_struct()
1819 ndev->ntb.topo = NTB_TOPO_NONE; in ndev_init_struct()
1820 ndev->ntb.ops = &intel_ntb_ops; in ndev_init_struct()
1822 ndev->b2b_off = 0; in ndev_init_struct()
1823 ndev->b2b_idx = UINT_MAX; in ndev_init_struct()
1825 ndev->bar4_split = 0; in ndev_init_struct()
1827 ndev->mw_count = 0; in ndev_init_struct()
1828 ndev->spad_count = 0; in ndev_init_struct()
1829 ndev->db_count = 0; in ndev_init_struct()
1830 ndev->db_vec_count = 0; in ndev_init_struct()
1831 ndev->db_vec_shift = 0; in ndev_init_struct()
1833 ndev->ntb_ctl = 0; in ndev_init_struct()
1834 ndev->lnk_sta = 0; in ndev_init_struct()
1836 ndev->db_valid_mask = 0; in ndev_init_struct()
1837 ndev->db_link_mask = 0; in ndev_init_struct()
1838 ndev->db_mask = 0; in ndev_init_struct()
1840 spin_lock_init(&ndev->db_mask_lock); in ndev_init_struct()
1849 node = dev_to_node(&pdev->dev); in intel_ntb_pci_probe()
1852 rc = -ENOMEM; in intel_ntb_pci_probe()
1867 ndev->ntb.ops = &intel_ntb3_ops; in intel_ntb_pci_probe()
1876 ndev->ntb.ops = &intel_ntb4_ops; in intel_ntb_pci_probe()
1885 rc = -EINVAL; in intel_ntb_pci_probe()
1891 ndev->reg->poll_link(ndev); in intel_ntb_pci_probe()
1895 rc = ntb_register_device(&ndev->ntb); in intel_ntb_pci_probe()
1899 dev_info(&pdev->dev, "NTB device registered.\n"); in intel_ntb_pci_probe()
1920 ntb_unregister_device(&ndev->ntb); in intel_ntb_pci_remove()
1960 * The secondary side cannot get the base address stored in primary
1961 * bars. The base address is necessary to set the limit register to
1964 * WITHOUT THE BASE ADDRESS, THE SECONDARY SIDE CANNOT DISABLE the
1965 * window by setting the limit equal to base, nor can it limit the size
1966 * of the memory window by setting the limit to base + size.