Lines Matching +full:msi +full:- +full:base +full:- +full:vec
8 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
17 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
65 #define NTB_DESC "AMD(R) PCI-E Non-Transparent Bridge Driver"
78 if (idx < 0 || idx > ndev->mw_count) in ndev_mw_to_bar()
79 return -EINVAL; in ndev_mw_to_bar()
81 return ndev->dev_data->mw_idx << idx; in ndev_mw_to_bar()
87 return -EINVAL; in amd_ntb_mw_count()
89 return ntb_ndev(ntb)->mw_count; in amd_ntb_mw_count()
101 return -EINVAL; in amd_ntb_mw_get_align()
114 *size_max = pci_resource_len(ndev->ntb.pdev, bar); in amd_ntb_mw_get_align()
130 return -EINVAL; in amd_ntb_mw_set_trans()
136 mw_size = pci_resource_len(ntb->pdev, bar); in amd_ntb_mw_set_trans()
140 return -EINVAL; in amd_ntb_mw_set_trans()
142 mmio = ndev->self_mmio; in amd_ntb_mw_set_trans()
143 peer_mmio = ndev->peer_mmio; in amd_ntb_mw_set_trans()
145 base_addr = pci_resource_start(ntb->pdev, bar); in amd_ntb_mw_set_trans()
148 xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2); in amd_ntb_mw_set_trans()
149 limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 2); in amd_ntb_mw_set_trans()
159 return -EIO; in amd_ntb_mw_set_trans()
168 return -EIO; in amd_ntb_mw_set_trans()
182 return -EIO; in amd_ntb_mw_set_trans()
191 return -EIO; in amd_ntb_mw_set_trans()
206 if (ndev->ntb.topo == NTB_TOPO_SEC) { in amd_ntb_get_link_status()
208 pci_swds = pci_upstream_bridge(ndev->ntb.pdev); in amd_ntb_get_link_status()
227 } else if (ndev->ntb.topo == NTB_TOPO_PRI) { in amd_ntb_get_link_status()
232 pdev = ndev->ntb.pdev; in amd_ntb_get_link_status()
241 ndev->lnk_sta = stat; in amd_ntb_get_link_status()
253 * - When a link-up event is received. This is indicated by in amd_link_is_up()
255 * - When driver on both sides of the link have been loaded. in amd_link_is_up()
262 * Now consider the sequence of events - Link-Up event occurs, in amd_link_is_up()
280 * the status of NTB secondary in this case, there is no Link-Up in amd_link_is_up()
281 * or Link-Down notification received. We recognize this condition in amd_link_is_up()
295 if (ndev->ntb.topo == NTB_TOPO_PRI) { in amd_link_is_up()
296 if ((ndev->peer_sta & AMD_LINK_UP_EVENT) || in amd_link_is_up()
297 (ndev->peer_sta == 0)) in amd_link_is_up()
299 else if (ndev->peer_sta & AMD_LINK_DOWN_EVENT) { in amd_link_is_up()
322 *speed = NTB_LNK_STA_SPEED(ndev->lnk_sta); in amd_ntb_link_is_up()
324 *width = NTB_LNK_STA_WIDTH(ndev->lnk_sta); in amd_ntb_link_is_up()
326 dev_dbg(&ntb->pdev->dev, "link is up.\n"); in amd_ntb_link_is_up()
335 dev_dbg(&ntb->pdev->dev, "link is down.\n"); in amd_ntb_link_is_up()
346 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_enable()
349 ndev->int_mask &= ~AMD_EVENT_INTMASK; in amd_ntb_link_enable()
350 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_enable()
352 if (ndev->ntb.topo == NTB_TOPO_SEC) in amd_ntb_link_enable()
353 return -EINVAL; in amd_ntb_link_enable()
354 dev_dbg(&ntb->pdev->dev, "Enabling Link.\n"); in amd_ntb_link_enable()
362 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_disable()
365 ndev->int_mask |= AMD_EVENT_INTMASK; in amd_ntb_link_disable()
366 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_disable()
368 if (ndev->ntb.topo == NTB_TOPO_SEC) in amd_ntb_link_disable()
369 return -EINVAL; in amd_ntb_link_disable()
370 dev_dbg(&ntb->pdev->dev, "Enabling Link.\n"); in amd_ntb_link_disable()
378 return ntb_ndev(ntb)->mw_count; in amd_ntb_peer_mw_count()
382 phys_addr_t *base, resource_size_t *size) in amd_ntb_peer_mw_get_addr() argument
391 if (base) in amd_ntb_peer_mw_get_addr()
392 *base = pci_resource_start(ndev->ntb.pdev, bar); in amd_ntb_peer_mw_get_addr()
395 *size = pci_resource_len(ndev->ntb.pdev, bar); in amd_ntb_peer_mw_get_addr()
402 return ntb_ndev(ntb)->db_valid_mask; in amd_ntb_db_valid_mask()
407 return ntb_ndev(ntb)->db_count; in amd_ntb_db_vector_count()
414 if (db_vector < 0 || db_vector > ndev->db_count) in amd_ntb_db_vector_mask()
417 return ntb_ndev(ntb)->db_valid_mask & (1ULL << db_vector); in amd_ntb_db_vector_mask()
423 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_read()
431 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_clear()
441 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_set_mask()
444 if (db_bits & ~ndev->db_valid_mask) in amd_ntb_db_set_mask()
445 return -EINVAL; in amd_ntb_db_set_mask()
447 spin_lock_irqsave(&ndev->db_mask_lock, flags); in amd_ntb_db_set_mask()
448 ndev->db_mask |= db_bits; in amd_ntb_db_set_mask()
449 writew((u16)ndev->db_mask, mmio + AMD_DBMASK_OFFSET); in amd_ntb_db_set_mask()
450 spin_unlock_irqrestore(&ndev->db_mask_lock, flags); in amd_ntb_db_set_mask()
458 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_clear_mask()
461 if (db_bits & ~ndev->db_valid_mask) in amd_ntb_db_clear_mask()
462 return -EINVAL; in amd_ntb_db_clear_mask()
464 spin_lock_irqsave(&ndev->db_mask_lock, flags); in amd_ntb_db_clear_mask()
465 ndev->db_mask &= ~db_bits; in amd_ntb_db_clear_mask()
466 writew((u16)ndev->db_mask, mmio + AMD_DBMASK_OFFSET); in amd_ntb_db_clear_mask()
467 spin_unlock_irqrestore(&ndev->db_mask_lock, flags); in amd_ntb_db_clear_mask()
475 void __iomem *mmio = ndev->self_mmio; in amd_ntb_peer_db_set()
484 return ntb_ndev(ntb)->spad_count; in amd_ntb_spad_count()
490 void __iomem *mmio = ndev->self_mmio; in amd_ntb_spad_read()
493 if (idx < 0 || idx >= ndev->spad_count) in amd_ntb_spad_read()
496 offset = ndev->self_spad + (idx << 2); in amd_ntb_spad_read()
504 void __iomem *mmio = ndev->self_mmio; in amd_ntb_spad_write()
507 if (idx < 0 || idx >= ndev->spad_count) in amd_ntb_spad_write()
508 return -EINVAL; in amd_ntb_spad_write()
510 offset = ndev->self_spad + (idx << 2); in amd_ntb_spad_write()
519 void __iomem *mmio = ndev->self_mmio; in amd_ntb_peer_spad_read()
522 if (sidx < 0 || sidx >= ndev->spad_count) in amd_ntb_peer_spad_read()
523 return -EINVAL; in amd_ntb_peer_spad_read()
525 offset = ndev->peer_spad + (sidx << 2); in amd_ntb_peer_spad_read()
533 void __iomem *mmio = ndev->self_mmio; in amd_ntb_peer_spad_write()
536 if (sidx < 0 || sidx >= ndev->spad_count) in amd_ntb_peer_spad_write()
537 return -EINVAL; in amd_ntb_peer_spad_write()
539 offset = ndev->peer_spad + (sidx << 2); in amd_ntb_peer_spad_write()
571 void __iomem *mmio = ndev->self_mmio; in amd_ack_smu()
579 static void amd_handle_event(struct amd_ntb_dev *ndev, int vec) in amd_handle_event() argument
581 void __iomem *mmio = ndev->self_mmio; in amd_handle_event()
582 struct device *dev = &ndev->ntb.pdev->dev; in amd_handle_event()
589 dev_dbg(dev, "status = 0x%x and vec = %d\n", status, vec); in amd_handle_event()
594 ndev->peer_sta |= AMD_PEER_FLUSH_EVENT; in amd_handle_event()
599 ndev->peer_sta |= status; in amd_handle_event()
601 ndev->peer_sta &= ~AMD_LINK_UP_EVENT; in amd_handle_event()
606 ntb_link_event(&ndev->ntb); in amd_handle_event()
608 schedule_delayed_work(&ndev->hb_timer, AMD_LINK_HB_TIMEOUT); in amd_handle_event()
614 ndev->peer_sta |= status; in amd_handle_event()
616 ndev->peer_sta &= ~AMD_LINK_DOWN_EVENT; in amd_handle_event()
618 ndev->peer_sta &= ~AMD_PEER_D0_EVENT; in amd_handle_event()
623 ntb_link_event(&ndev->ntb); in amd_handle_event()
627 mmio = ndev->peer_mmio; in amd_handle_event()
633 ndev->peer_sta |= AMD_PEER_D0_EVENT; in amd_handle_event()
634 ndev->peer_sta &= ~AMD_PEER_D3_EVENT; in amd_handle_event()
638 schedule_delayed_work(&ndev->hb_timer, in amd_handle_event()
650 static void amd_handle_db_event(struct amd_ntb_dev *ndev, int vec) in amd_handle_db_event() argument
652 struct device *dev = &ndev->ntb.pdev->dev; in amd_handle_db_event()
655 status = amd_ntb_db_read(&ndev->ntb); in amd_handle_db_event()
657 dev_dbg(dev, "status = 0x%llx and vec = %d\n", status, vec); in amd_handle_db_event()
664 if (status & BIT(ndev->db_last_bit)) { in amd_handle_db_event()
665 ntb_db_clear(&ndev->ntb, BIT(ndev->db_last_bit)); in amd_handle_db_event()
667 ntb_link_event(&ndev->ntb); in amd_handle_db_event()
672 * un-loaded for some reason. Since there is a chance that the in amd_handle_db_event()
676 schedule_delayed_work(&ndev->hb_timer, AMD_LINK_HB_TIMEOUT); in amd_handle_db_event()
680 static irqreturn_t ndev_interrupt(struct amd_ntb_dev *ndev, int vec) in ndev_interrupt() argument
682 dev_dbg(&ndev->ntb.pdev->dev, "vec %d\n", vec); in ndev_interrupt()
684 if (vec > (AMD_DB_CNT - 1) || (ndev->msix_vec_count == 1)) in ndev_interrupt()
685 amd_handle_event(ndev, vec); in ndev_interrupt()
687 if (vec < AMD_DB_CNT) { in ndev_interrupt()
688 amd_handle_db_event(ndev, vec); in ndev_interrupt()
689 ntb_db_event(&ndev->ntb, vec); in ndev_interrupt()
699 return ndev_interrupt(nvec->ndev, nvec->num); in ndev_vec_isr()
706 return ndev_interrupt(ndev, irq - ndev->ntb.pdev->irq); in ndev_irq_isr()
715 pdev = ndev->ntb.pdev; in ndev_init_isr()
717 node = dev_to_node(&pdev->dev); in ndev_init_isr()
719 ndev->db_mask = ndev->db_valid_mask; in ndev_init_isr()
722 ndev->vec = kcalloc_node(msix_max, sizeof(*ndev->vec), in ndev_init_isr()
724 if (!ndev->vec) in ndev_init_isr()
727 ndev->msix = kcalloc_node(msix_max, sizeof(*ndev->msix), in ndev_init_isr()
729 if (!ndev->msix) in ndev_init_isr()
733 ndev->msix[i].entry = i; in ndev_init_isr()
735 msix_count = pci_enable_msix_range(pdev, ndev->msix, in ndev_init_isr()
749 ndev->vec[i].ndev = ndev; in ndev_init_isr()
750 ndev->vec[i].num = i; in ndev_init_isr()
751 rc = request_irq(ndev->msix[i].vector, ndev_vec_isr, 0, in ndev_init_isr()
752 "ndev_vec_isr", &ndev->vec[i]); in ndev_init_isr()
757 dev_dbg(&pdev->dev, "Using msix interrupts\n"); in ndev_init_isr()
758 ndev->db_count = msix_min; in ndev_init_isr()
759 ndev->msix_vec_count = msix_max; in ndev_init_isr()
763 while (i-- > 0) in ndev_init_isr()
764 free_irq(ndev->msix[i].vector, &ndev->vec[i]); in ndev_init_isr()
767 kfree(ndev->msix); in ndev_init_isr()
769 kfree(ndev->vec); in ndev_init_isr()
771 ndev->msix = NULL; in ndev_init_isr()
772 ndev->vec = NULL; in ndev_init_isr()
774 /* Try to set up msi irq */ in ndev_init_isr()
779 rc = request_irq(pdev->irq, ndev_irq_isr, 0, in ndev_init_isr()
784 dev_dbg(&pdev->dev, "Using msi interrupts\n"); in ndev_init_isr()
785 ndev->db_count = 1; in ndev_init_isr()
786 ndev->msix_vec_count = 1; in ndev_init_isr()
796 rc = request_irq(pdev->irq, ndev_irq_isr, IRQF_SHARED, in ndev_init_isr()
801 dev_dbg(&pdev->dev, "Using intx interrupts\n"); in ndev_init_isr()
802 ndev->db_count = 1; in ndev_init_isr()
803 ndev->msix_vec_count = 1; in ndev_init_isr()
813 void __iomem *mmio = ndev->self_mmio; in ndev_deinit_isr()
816 pdev = ndev->ntb.pdev; in ndev_deinit_isr()
819 ndev->db_mask = ndev->db_valid_mask; in ndev_deinit_isr()
820 writel(ndev->db_mask, mmio + AMD_DBMASK_OFFSET); in ndev_deinit_isr()
822 if (ndev->msix) { in ndev_deinit_isr()
823 i = ndev->msix_vec_count; in ndev_deinit_isr()
824 while (i--) in ndev_deinit_isr()
825 free_irq(ndev->msix[i].vector, &ndev->vec[i]); in ndev_deinit_isr()
827 kfree(ndev->msix); in ndev_deinit_isr()
828 kfree(ndev->vec); in ndev_deinit_isr()
830 free_irq(pdev->irq, ndev); in ndev_deinit_isr()
848 ndev = filp->private_data; in ndev_debugfs_read()
849 mmio = ndev->self_mmio; in ndev_debugfs_read()
855 return -ENOMEM; in ndev_debugfs_read()
859 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
862 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
863 "Connection Topology -\t%s\n", in ndev_debugfs_read()
864 ntb_topo_string(ndev->ntb.topo)); in ndev_debugfs_read()
866 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
867 "LNK STA -\t\t%#06x\n", ndev->lnk_sta); in ndev_debugfs_read()
870 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
871 "Link Status -\t\tDown\n"); in ndev_debugfs_read()
873 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
874 "Link Status -\t\tUp\n"); in ndev_debugfs_read()
875 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
876 "Link Speed -\t\tPCI-E Gen %u\n", in ndev_debugfs_read()
877 NTB_LNK_STA_SPEED(ndev->lnk_sta)); in ndev_debugfs_read()
878 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
879 "Link Width -\t\tx%u\n", in ndev_debugfs_read()
880 NTB_LNK_STA_WIDTH(ndev->lnk_sta)); in ndev_debugfs_read()
883 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
884 "Memory Window Count -\t%u\n", ndev->mw_count); in ndev_debugfs_read()
885 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
886 "Scratchpad Count -\t%u\n", ndev->spad_count); in ndev_debugfs_read()
887 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
888 "Doorbell Count -\t%u\n", ndev->db_count); in ndev_debugfs_read()
889 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
890 "MSIX Vector Count -\t%u\n", ndev->msix_vec_count); in ndev_debugfs_read()
892 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
893 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask); in ndev_debugfs_read()
895 u.v32 = readl(ndev->self_mmio + AMD_DBMASK_OFFSET); in ndev_debugfs_read()
896 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
897 "Doorbell Mask -\t\t\t%#06x\n", u.v32); in ndev_debugfs_read()
900 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
901 "Doorbell Bell -\t\t\t%#06x\n", u.v32); in ndev_debugfs_read()
903 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
907 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
908 "XLAT1 -\t\t%#018llx\n", u.v64); in ndev_debugfs_read()
910 u.v64 = read64(ndev->self_mmio + AMD_BAR23XLAT_OFFSET); in ndev_debugfs_read()
911 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
912 "XLAT23 -\t\t%#018llx\n", u.v64); in ndev_debugfs_read()
914 u.v64 = read64(ndev->self_mmio + AMD_BAR45XLAT_OFFSET); in ndev_debugfs_read()
915 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
916 "XLAT45 -\t\t%#018llx\n", u.v64); in ndev_debugfs_read()
919 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
920 "LMT1 -\t\t\t%#06x\n", u.v32); in ndev_debugfs_read()
922 u.v64 = read64(ndev->self_mmio + AMD_BAR23LMT_OFFSET); in ndev_debugfs_read()
923 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
924 "LMT23 -\t\t\t%#018llx\n", u.v64); in ndev_debugfs_read()
926 u.v64 = read64(ndev->self_mmio + AMD_BAR45LMT_OFFSET); in ndev_debugfs_read()
927 off += scnprintf(buf + off, buf_size - off, in ndev_debugfs_read()
928 "LMT45 -\t\t\t%#018llx\n", u.v64); in ndev_debugfs_read()
938 ndev->debugfs_dir = NULL; in ndev_init_debugfs()
939 ndev->debugfs_info = NULL; in ndev_init_debugfs()
941 ndev->debugfs_dir = in ndev_init_debugfs()
942 debugfs_create_dir(pci_name(ndev->ntb.pdev), in ndev_init_debugfs()
944 ndev->debugfs_info = in ndev_init_debugfs()
946 ndev->debugfs_dir, ndev, in ndev_init_debugfs()
953 debugfs_remove_recursive(ndev->debugfs_dir); in ndev_deinit_debugfs()
959 ndev->ntb.pdev = pdev; in ndev_init_struct()
960 ndev->ntb.topo = NTB_TOPO_NONE; in ndev_init_struct()
961 ndev->ntb.ops = &amd_ntb_ops; in ndev_init_struct()
962 ndev->int_mask = AMD_EVENT_INTMASK; in ndev_init_struct()
963 spin_lock_init(&ndev->db_mask_lock); in ndev_init_struct()
968 void __iomem *mmio = ndev->peer_mmio; in amd_poll_link()
974 dev_dbg(&ndev->ntb.pdev->dev, "%s: reg_val = 0x%x.\n", __func__, reg); in amd_poll_link()
976 ndev->cntl_sta = reg; in amd_poll_link()
980 return ndev->cntl_sta; in amd_poll_link()
988 ntb_link_event(&ndev->ntb); in amd_link_hb()
991 schedule_delayed_work(&ndev->hb_timer, AMD_LINK_HB_TIMEOUT); in amd_link_hb()
1005 mmio = ndev->peer_mmio; in amd_set_side_info_reg()
1007 mmio = ndev->self_mmio; in amd_set_side_info_reg()
1022 mmio = ndev->peer_mmio; in amd_clear_side_info_reg()
1024 mmio = ndev->self_mmio; in amd_clear_side_info_reg()
1036 void __iomem *mmio = ndev->self_mmio; in amd_init_side_info()
1048 void __iomem *mmio = ndev->self_mmio; in amd_deinit_side_info()
1060 void __iomem *mmio = ndev->self_mmio; in amd_init_ntb()
1062 ndev->mw_count = ndev->dev_data->mw_count; in amd_init_ntb()
1063 ndev->spad_count = AMD_SPADS_CNT; in amd_init_ntb()
1064 ndev->db_count = AMD_DB_CNT; in amd_init_ntb()
1066 switch (ndev->ntb.topo) { in amd_init_ntb()
1069 ndev->spad_count >>= 1; in amd_init_ntb()
1070 if (ndev->ntb.topo == NTB_TOPO_PRI) { in amd_init_ntb()
1071 ndev->self_spad = 0; in amd_init_ntb()
1072 ndev->peer_spad = 0x20; in amd_init_ntb()
1074 ndev->self_spad = 0x20; in amd_init_ntb()
1075 ndev->peer_spad = 0; in amd_init_ntb()
1078 INIT_DELAYED_WORK(&ndev->hb_timer, amd_link_hb); in amd_init_ntb()
1079 schedule_delayed_work(&ndev->hb_timer, AMD_LINK_HB_TIMEOUT); in amd_init_ntb()
1083 dev_err(&ndev->ntb.pdev->dev, in amd_init_ntb()
1085 return -EINVAL; in amd_init_ntb()
1089 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_init_ntb()
1096 void __iomem *mmio = ndev->self_mmio; in amd_get_topo()
1108 void __iomem *mmio = ndev->self_mmio; in amd_init_dev()
1112 pdev = ndev->ntb.pdev; in amd_init_dev()
1114 ndev->ntb.topo = amd_get_topo(ndev); in amd_init_dev()
1115 dev_dbg(&pdev->dev, "AMD NTB topo is %s\n", in amd_init_dev()
1116 ntb_topo_string(ndev->ntb.topo)); in amd_init_dev()
1124 dev_err(&pdev->dev, "fail to init isr.\n"); in amd_init_dev()
1128 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; in amd_init_dev()
1132 * un-loaded. in amd_init_dev()
1134 ndev->db_last_bit = in amd_init_dev()
1135 find_last_bit((unsigned long *)&ndev->db_valid_mask, in amd_init_dev()
1136 hweight64(ndev->db_valid_mask)); in amd_init_dev()
1137 writew((u16)~BIT(ndev->db_last_bit), mmio + AMD_DBMASK_OFFSET); in amd_init_dev()
1142 ndev->db_count -= 1; in amd_init_dev()
1143 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; in amd_init_dev()
1145 /* Enable Link-Up and Link-Down event interrupts */ in amd_init_dev()
1146 ndev->int_mask &= ~(AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT); in amd_init_dev()
1147 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_init_dev()
1154 cancel_delayed_work_sync(&ndev->hb_timer); in amd_deinit_dev()
1176 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in amd_ntb_init_pci()
1178 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in amd_ntb_init_pci()
1181 dev_warn(&pdev->dev, "Cannot DMA highmem\n"); in amd_ntb_init_pci()
1184 ndev->self_mmio = pci_iomap(pdev, 0, 0); in amd_ntb_init_pci()
1185 if (!ndev->self_mmio) { in amd_ntb_init_pci()
1186 rc = -EIO; in amd_ntb_init_pci()
1189 ndev->peer_mmio = ndev->self_mmio + AMD_PEER_OFFSET; in amd_ntb_init_pci()
1204 struct pci_dev *pdev = ndev->ntb.pdev; in amd_ntb_deinit_pci()
1206 pci_iounmap(pdev, ndev->self_mmio); in amd_ntb_deinit_pci()
1219 node = dev_to_node(&pdev->dev); in amd_ntb_pci_probe()
1223 rc = -ENOMEM; in amd_ntb_pci_probe()
1227 ndev->dev_data = (struct ntb_dev_data *)id->driver_data; in amd_ntb_pci_probe()
1246 rc = ntb_register_device(&ndev->ntb); in amd_ntb_pci_probe()
1250 dev_info(&pdev->dev, "NTB device registered.\n"); in amd_ntb_pci_probe()
1275 ntb_peer_db_set(&ndev->ntb, BIT_ULL(ndev->db_last_bit)); in amd_ntb_pci_remove()
1276 ntb_unregister_device(&ndev->ntb); in amd_ntb_pci_remove()
1288 ntb_link_event(&ndev->ntb); in amd_ntb_pci_shutdown()
1291 ntb_peer_db_set(&ndev->ntb, BIT_ULL(ndev->db_last_bit)); in amd_ntb_pci_shutdown()
1292 ntb_unregister_device(&ndev->ntb); in amd_ntb_pci_shutdown()