Lines Matching +full:0 +full:x2008

34 #define PORT_CH_ID_MASK		GENMASK(7, 0)
37  * The channel number consists of peer_id(15:12) , channel_id(11:0)
39  * 0:reserved, 1: to AP, 2: to MD
43 	PORT_CH_AP_CONTROL_RX = 0x1000,
44 	PORT_CH_AP_CONTROL_TX = 0x1001,
47 	PORT_CH_CONTROL_RX = 0x2000,
48 	PORT_CH_CONTROL_TX = 0x2001,
49 	PORT_CH_UART1_RX = 0x2006,	/* META */
50 	PORT_CH_UART1_TX = 0x2008,
51 	PORT_CH_UART2_RX = 0x200a,	/* AT */
52 	PORT_CH_UART2_TX = 0x200c,
53 	PORT_CH_MD_LOG_RX = 0x202a,	/* MD logging */
54 	PORT_CH_MD_LOG_TX = 0x202b,
55 	PORT_CH_LB_IT_RX = 0x203e,	/* Loop back test */
56 	PORT_CH_LB_IT_TX = 0x203f,
57 	PORT_CH_STATUS_RX = 0x2043,	/* Status events */
58 	PORT_CH_MIPC_RX = 0x20ce,	/* MIPC */
59 	PORT_CH_MIPC_TX = 0x20cf,
60 	PORT_CH_MBIM_RX = 0x20d0,
61 	PORT_CH_MBIM_TX = 0x20d1,
62 	PORT_CH_DSS0_RX = 0x20d2,
63 	PORT_CH_DSS0_TX = 0x20d3,
64 	PORT_CH_DSS1_RX = 0x20d4,
65 	PORT_CH_DSS1_TX = 0x20d5,
66 	PORT_CH_DSS2_RX = 0x20d6,
67 	PORT_CH_DSS2_TX = 0x20d7,
68 	PORT_CH_DSS3_RX = 0x20d8,
69 	PORT_CH_DSS3_TX = 0x20d9,
70 	PORT_CH_DSS4_RX = 0x20da,
71 	PORT_CH_DSS4_TX = 0x20db,
72 	PORT_CH_DSS5_RX = 0x20dc,
73 	PORT_CH_DSS5_TX = 0x20dd,
74 	PORT_CH_DSS6_RX = 0x20de,
75 	PORT_CH_DSS6_TX = 0x20df,
76 	PORT_CH_DSS7_RX = 0x20e0,
77 	PORT_CH_DSS7_TX = 0x20e1,
79 	PORT_CH_UNIMPORTANT = 0xffff,