150 	void __iomem *ctrl_reg = IREG_BASE(t7xx_dev) + T7XX_PCIE_MISC_CTRL;  in t7xx_dev_set_sleep_capability()
170 				IREG_BASE(t7xx_dev) + T7XX_PCIE_RESOURCE_STATUS);  in t7xx_wait_pm_config()
193 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);  in t7xx_pci_pm_init()
209 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in t7xx_pci_pm_init_late()
227 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);  in t7xx_pci_pm_reinit()
233 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);  in t7xx_pci_pm_exp_detected()
310 		status = ioread32(IREG_BASE(t7xx_dev) + T7XX_PCIE_RESOURCE_STATUS);  in t7xx_pci_disable_sleep()
374 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);  in __t7xx_pci_pm_suspend()
377 		iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in __t7xx_pci_pm_suspend()
415 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in __t7xx_pci_pm_suspend()
427 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in __t7xx_pci_pm_suspend()
438 	iowrite32(MSIX_MSK_SET_ALL, IREG_BASE(t7xx_dev) + IMASK_HOST_MSIX_CLR_GRP0_0);  in t7xx_pcie_interrupt_reinit()
531 		iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in __t7xx_pci_pm_resume()
536 	prev_state = ioread32(IREG_BASE(t7xx_dev) + T7XX_PCIE_PM_RESUME_STATE);  in __t7xx_pci_pm_resume()
543 		u32 atr_reg_val = ioread32(IREG_BASE(t7xx_dev) +  in __t7xx_pci_pm_resume()
594 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);  in __t7xx_pci_pm_resume()
621 	iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in __t7xx_pci_pm_resume()
824 	IREG_BASE(t7xx_dev) = pcim_iomap_table(pdev)[T7XX_PCI_IREG_BASE];  in t7xx_pci_probe()