299 static void t7xx_cldma_exception(struct cldma_ctrl *md_ctrl, enum hif_ex_stage stage)  in t7xx_cldma_exception()  argument
303 		t7xx_cldma_stop_all_qs(md_ctrl, MTK_TX);  in t7xx_cldma_exception()
304 		t7xx_cldma_clear_all_qs(md_ctrl, MTK_TX);  in t7xx_cldma_exception()
311 		t7xx_cldma_stop_all_qs(md_ctrl, MTK_RX);  in t7xx_cldma_exception()
312 		t7xx_cldma_stop(md_ctrl);  in t7xx_cldma_exception()
314 		if (md_ctrl->hif_id == CLDMA_ID_MD)  in t7xx_cldma_exception()
315 			t7xx_cldma_hw_reset(md_ctrl->t7xx_dev->base_addr.infracfg_ao_base);  in t7xx_cldma_exception()
317 		t7xx_cldma_clear_all_qs(md_ctrl, MTK_RX);  in t7xx_cldma_exception()
321 		t7xx_cldma_hw_init(&md_ctrl->hw_info);  in t7xx_cldma_exception()
322 		t7xx_cldma_start(md_ctrl);  in t7xx_cldma_exception()
340 	t7xx_cldma_exception(md->md_ctrl[CLDMA_ID_MD], stage);  in t7xx_md_exception()
341 	t7xx_cldma_exception(md->md_ctrl[CLDMA_ID_AP], stage);  in t7xx_md_exception()
571 	t7xx_cldma_switch_cfg(md->md_ctrl[CLDMA_ID_MD], CLDMA_SHARED_Q_CFG);  in t7xx_md_hk_wq()
572 	t7xx_cldma_start(md->md_ctrl[CLDMA_ID_MD]);  in t7xx_md_hk_wq()
585 	t7xx_cldma_stop(md->md_ctrl[CLDMA_ID_AP]);  in t7xx_ap_hk_wq()
586 	t7xx_cldma_switch_cfg(md->md_ctrl[CLDMA_ID_AP], CLDMA_SHARED_Q_CFG);  in t7xx_ap_hk_wq()
587 	t7xx_cldma_start(md->md_ctrl[CLDMA_ID_AP]);  in t7xx_ap_hk_wq()
714 	t7xx_cldma_reset(md->md_ctrl[CLDMA_ID_MD]);  in t7xx_md_reset()
715 	t7xx_cldma_reset(md->md_ctrl[CLDMA_ID_AP]);  in t7xx_md_reset()
757 	ret = t7xx_cldma_init(md->md_ctrl[CLDMA_ID_MD]);  in t7xx_md_init()
761 	ret = t7xx_cldma_init(md->md_ctrl[CLDMA_ID_AP]);  in t7xx_md_init()
781 	t7xx_cldma_exit(md->md_ctrl[CLDMA_ID_AP]);  in t7xx_md_init()
784 	t7xx_cldma_exit(md->md_ctrl[CLDMA_ID_MD]);  in t7xx_md_init()
811 	t7xx_cldma_exit(md->md_ctrl[CLDMA_ID_AP]);  in t7xx_md_exit()
812 	t7xx_cldma_exit(md->md_ctrl[CLDMA_ID_MD]);  in t7xx_md_exit()