32 static void t7xx_mhccif_clear_interrupts(struct t7xx_pci_dev *t7xx_dev, u32 mask)  in t7xx_mhccif_clear_interrupts()  argument
34 	void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;  in t7xx_mhccif_clear_interrupts()
39 	t7xx_mhccif_read_sw_int_sts(t7xx_dev);  in t7xx_mhccif_clear_interrupts()
41 	t7xx_pcie_mac_clear_int_status(t7xx_dev, MHCCIF_INT);  in t7xx_mhccif_clear_interrupts()
46 	struct t7xx_pci_dev *t7xx_dev = data;  in t7xx_mhccif_isr_thread()  local
50 	iowrite32(val, IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);  in t7xx_mhccif_isr_thread()
52 	int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);  in t7xx_mhccif_isr_thread()
54 		int ret = t7xx_pci_mhccif_isr(t7xx_dev);  in t7xx_mhccif_isr_thread()
57 			dev_err(&t7xx_dev->pdev->dev, "PCI MHCCIF ISR failure: %d", ret);  in t7xx_mhccif_isr_thread()
60 	t7xx_mhccif_clear_interrupts(t7xx_dev, int_status);  in t7xx_mhccif_isr_thread()
63 		complete_all(&t7xx_dev->sleep_lock_acquire);  in t7xx_mhccif_isr_thread()
66 		complete(&t7xx_dev->pm_sr_ack);  in t7xx_mhccif_isr_thread()
68 	iowrite32(T7XX_L1_BIT(1), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in t7xx_mhccif_isr_thread()
70 	int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);  in t7xx_mhccif_isr_thread()
73 		iowrite32(val, IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);  in t7xx_mhccif_isr_thread()
76 	t7xx_pcie_mac_set_int(t7xx_dev, MHCCIF_INT);  in t7xx_mhccif_isr_thread()
80 u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev)  in t7xx_mhccif_read_sw_int_sts()  argument
82 	return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_STS);  in t7xx_mhccif_read_sw_int_sts()
85 void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val)  in t7xx_mhccif_mask_set()  argument
87 	iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_SET);  in t7xx_mhccif_mask_set()
90 void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val)  in t7xx_mhccif_mask_clr()  argument
92 	iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR);  in t7xx_mhccif_mask_clr()
95 u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev)  in t7xx_mhccif_mask_get()  argument
97 	return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK);  in t7xx_mhccif_mask_get()
105 void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev)  in t7xx_mhccif_init()  argument
107 	t7xx_dev->base_addr.mhccif_rc_base = t7xx_dev->base_addr.pcie_ext_reg_base +  in t7xx_mhccif_init()
109 					    t7xx_dev->base_addr.pcie_dev_reg_trsl_addr;  in t7xx_mhccif_init()
111 	t7xx_dev->intr_handler[MHCCIF_INT] = t7xx_mhccif_isr_handler;  in t7xx_mhccif_init()
112 	t7xx_dev->intr_thread[MHCCIF_INT] = t7xx_mhccif_isr_thread;  in t7xx_mhccif_init()
113 	t7xx_dev->callback_param[MHCCIF_INT] = t7xx_dev;  in t7xx_mhccif_init()
116 void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel)  in t7xx_mhccif_h2d_swint_trigger()  argument
118 	void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;  in t7xx_mhccif_h2d_swint_trigger()