225 					 unsigned int intr_status,  in t7xx_dpmaif_hw_check_tx_intr()  argument
230 	value = FIELD_GET(DP_UL_INT_QDONE_MSK, intr_status);  in t7xx_dpmaif_hw_check_tx_intr()
240 	value = FIELD_GET(DP_UL_INT_EMPTY_MSK, intr_status);  in t7xx_dpmaif_hw_check_tx_intr()
244 	value = FIELD_GET(DP_UL_INT_MD_NOTREADY_MSK, intr_status);  in t7xx_dpmaif_hw_check_tx_intr()
248 	value = FIELD_GET(DP_UL_INT_MD_PWR_NOTREADY_MSK, intr_status);  in t7xx_dpmaif_hw_check_tx_intr()
252 	value = FIELD_GET(DP_UL_INT_ERR_MSK, intr_status);  in t7xx_dpmaif_hw_check_tx_intr()
257 	iowrite32(intr_status, hw_info->pcie_base + DPMAIF_AP_L2TISAR0);  in t7xx_dpmaif_hw_check_tx_intr()
264 					 unsigned int intr_status,  in t7xx_dpmaif_hw_check_rx_intr()  argument
268 		if (intr_status & DP_DL_INT_SKB_LEN_ERR)  in t7xx_dpmaif_hw_check_rx_intr()
271 		if (intr_status & DP_DL_INT_BATCNT_LEN_ERR) {  in t7xx_dpmaif_hw_check_rx_intr()
278 		if (intr_status & DP_DL_INT_PITCNT_LEN_ERR) {  in t7xx_dpmaif_hw_check_rx_intr()
285 		if (intr_status & DP_DL_INT_PKT_EMPTY_MSK)  in t7xx_dpmaif_hw_check_rx_intr()
288 		if (intr_status & DP_DL_INT_FRG_EMPTY_MSK)  in t7xx_dpmaif_hw_check_rx_intr()
291 		if (intr_status & DP_DL_INT_MTU_ERR_MSK)  in t7xx_dpmaif_hw_check_rx_intr()
294 		if (intr_status & DP_DL_INT_FRG_LEN_ERR_MSK)  in t7xx_dpmaif_hw_check_rx_intr()
297 		if (intr_status & DP_DL_INT_Q0_PITCNT_LEN_ERR) {  in t7xx_dpmaif_hw_check_rx_intr()
302 		if (intr_status & DP_DL_INT_HPC_ENT_TYPE_ERR)  in t7xx_dpmaif_hw_check_rx_intr()
306 		if (intr_status & DP_DL_INT_Q0_DONE) {  in t7xx_dpmaif_hw_check_rx_intr()
313 				intr_status &= ~DP_DL_INT_Q0_DONE;  in t7xx_dpmaif_hw_check_rx_intr()
316 		if (intr_status & DP_DL_INT_Q1_PITCNT_LEN_ERR) {  in t7xx_dpmaif_hw_check_rx_intr()
321 		if (intr_status & DP_DL_INT_Q1_DONE) {  in t7xx_dpmaif_hw_check_rx_intr()
325 				intr_status &= ~DP_DL_INT_Q1_DONE;  in t7xx_dpmaif_hw_check_rx_intr()
329 	intr_status |= DP_DL_INT_BATCNT_LEN_ERR;  in t7xx_dpmaif_hw_check_rx_intr()
331 	iowrite32(intr_status, hw_info->pcie_base + DPMAIF_AP_APDL_L2TISAR0);  in t7xx_dpmaif_hw_check_rx_intr()
1271 	u32 intr_status;  in t7xx_dpmaif_ul_clr_done()  local
1273 	intr_status = ioread32(hw_info->pcie_base + DPMAIF_AP_L2TISAR0);  in t7xx_dpmaif_ul_clr_done()
1274 	intr_status &= BIT(DP_UL_INT_DONE_OFFSET + qno);  in t7xx_dpmaif_ul_clr_done()
1275 	if (intr_status) {  in t7xx_dpmaif_ul_clr_done()
1276 		iowrite32(intr_status, hw_info->pcie_base + DPMAIF_AP_L2TISAR0);  in t7xx_dpmaif_ul_clr_done()