32 	val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);  in t7xx_cldma_clear_ip_busy()
34 	iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);  in t7xx_cldma_clear_ip_busy()
47 	ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);  in t7xx_cldma_hw_restore()
57 	iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);  in t7xx_cldma_hw_restore()
59 	iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);  in t7xx_cldma_hw_restore()
60 	iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);  in t7xx_cldma_hw_restore()
69 	reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD :  in t7xx_cldma_hw_start_queue()
70 				hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD;  in t7xx_cldma_hw_start_queue()
78 	iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);  in t7xx_cldma_hw_start()
81 	iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);  in t7xx_cldma_hw_start()
109 	return ioread64_lo_hi(hw_info->ap_pdn_base + offset);  in t7xx_cldma_tx_addr_is_set()
119 				hw_info->ap_pdn_base + REG_CLDMA_UL_START_ADDRL_0;  in t7xx_cldma_hw_set_start_addr()
126 	void __iomem *base = hw_info->ap_pdn_base;  in t7xx_cldma_hw_resume_queue()
142 				hw_info->ap_pdn_base + REG_CLDMA_UL_STATUS;  in t7xx_cldma_hw_queue_status()
152 	ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);  in t7xx_cldma_hw_tx_done()
155 	iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);  in t7xx_cldma_hw_tx_done()
156 	ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);  in t7xx_cldma_hw_tx_done()
163 	ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);  in t7xx_cldma_hw_rx_done()
166 	iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);  in t7xx_cldma_hw_rx_done()
167 	ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);  in t7xx_cldma_hw_rx_done()
176 	reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0 :  in t7xx_cldma_hw_int_status()
177 				hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0;  in t7xx_cldma_hw_int_status()
189 				hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;  in t7xx_cldma_hw_irq_dis_txrx()
200 				hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;  in t7xx_cldma_hw_irq_dis_eq()
212 				hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;  in t7xx_cldma_hw_irq_en_txrx()
223 				hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;  in t7xx_cldma_hw_irq_en_eq()
238 	ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);  in t7xx_cldma_hw_init()
255 	iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);  in t7xx_cldma_hw_init()
260 	iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);  in t7xx_cldma_hw_init()
261 	iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);  in t7xx_cldma_hw_init()
268 	reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_STOP_CMD :  in t7xx_cldma_hw_stop_all_qs()
269 				hw_info->ap_pdn_base + REG_CLDMA_UL_STOP_CMD;  in t7xx_cldma_hw_stop_all_qs()
278 				hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;  in t7xx_cldma_hw_stop()